tag: CFET

A Comprehensive Study Of Integrating 2D Materials With CFET Architecture (SKKU, et al.)
By Technical Paper Link - 12 May, 2026 - Comments: 0

A new technical paper, "Challenges and prospects of 2D electronics for future monolithic complementary field-effect transistors," was published by researchers at Sungkyunkwan University, Hanyang University, Istituto Italiano di Tecnologia, Shanghai University, Jeonbuk National University, and Kyonggi University. Abstract "With planar complementary metal-oxide-semiconductor (CMOS) scaling ... » read more

Vertically Stacked ZnO/Te CFETs (POSTECH, Mokpo)
By Technical Paper Link - 09 Jun, 2025 - Comments: 0

A new technical paper titled "Demonstration of Vertically Stacked ZnO/Te Complementary Field-Effect Transistor" was published by researchers at POSTECH and Mokpo National University. Abstract "The complementary field-effect transistor (CFET) structure is a highly area-efficient technology. However, their fabrication entails highly complex integration processes using wafer transfer or recr... » read more

CFETs: Reliability of Complementary Field-Effect Transistors (TU Munich, IIT)
By Technical Paper Link - 14 May, 2025 - Comments: 0

A technical paper titled "CFET Beyond 3 nm: SRAM Reliability under Design-Time and Run-Time Variability" was published by researchers at TU Munich and IIT Kanpur. Abstract "This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging ef... » read more

Design Optimization Techniques To Improve NC-CFET Performance
By Technical Paper Link - 14 Mar, 2025 - Comments: 0

A new technical paper titled "Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configu... » read more

CFETs with Optimized Buried Power Rails
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A technical paper titled "Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET)" was published by researchers at Korea University and Sungkyunkwan University. Abstract "In the pursuit of minimizing the track height in standard cell, a design innovation incorporating complementary field-effect transistors (CFETs) and Buried Power Rail (BPR) technolog... » read more

Understanding CFETs, A Next Generation Transistor Architecture
By Sam Sarkar - 23 May, 2024 - Comments: 0

Computing power has experienced exponential growth over the last 70 years. This has largely been achieved through transistor scaling. Due to a continuous reduction in the size of transistors, engineers have been able to pack more and more of them onto a single chip [1]. This has led to faster, more powerful, and more energy-efficient devices. Improvements in fabrication processes and materials,... » read more

Building CFETs With Monolithic And Sequential 3D
By Katherine Derbyshire - 22 Feb, 2024 - Comments: 0

Successive versions of vertical transistors are emerging as the likely successor to finFETs, combining lower leakage with significant area reduction. A stacked nanosheet transistor, introduced at N3, uses multiple channel layers to maintain the overall channel length and necessary drive current while continuing to reduce the standard cell footprint. The follow-on technology, the CFET, pushes... » read more

Full Wafer Integration of Aggressively Scaled 2D-Based Logic Circuits (Imec)
By Technical Paper Link - 28 Oct, 2022 - Comments: 0

A technical paper titled "Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits" was published by researchers at Imec. "The introduction of highly scaled 2D-based circuits for high-performance logic applications in production is projected to be implemented after the Si-sheet-based CFET devices. Here, a view on the requirements needed for full waf... » read more

Week In Review: Manufacturing, Test
By Ed Sperling - 17 Jun, 2022 - Comments: 0

Node scaling wars are revving up, although much of the action is happening where most people can't see it — inside of research labs. This is difficult stuff, which makes delivery dates difficult to pinpoint, and no one wants to give away their competitive position or commit to a timeline they can't keep. Billions of dollars of leading-edge research — funded by pure-play foundry TSMC, IDM... » read more

Manufacturing Bits: Nov. 17
By Mark LaPedus - 17 Nov, 2020 - Comments: 0

Intel’s gate-all-around FETs At the upcoming IEEE International Electron Devices Meeting (IEDM), Intel is expected to present papers on its efforts to develop gate-all-around transistors. One paper from Intel describes a more conventional gate-all-around transistor technology called a nanosheet FET. Another paper involves a next-generation NMOS-on-PMOS nanoribbon transistor technology. (F... » read more

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