Week In Review: Manufacturing, Test

Node scaling wars rev up; CFETs; CNT FETs; bismuth and antimony; Applied’s acquisition; power delivery schemes; 123 leaders hit D.C.; MCUs; quantum.


Node scaling wars are revving up, although much of the action is happening where most people can’t see it — inside of research labs. This is difficult stuff, which makes delivery dates difficult to pinpoint, and no one wants to give away their competitive position or commit to a timeline they can’t keep.

Billions of dollars of leading-edge research — funded by pure-play foundry TSMC, IDMs Intel and Samsung, and non-profit research house Imec — are pouring into the development of new transistor structures that will extend from the nanometer scale into the angstrom scale over the next decade.

Nanosheets (also known as gate-all-around FETs), will succeed finFETs over the course of the next half-decade. TSMC said this week it will introduce nanosheets at 2nm. Samsung will use them at 3nm. And Intel will introduce them at 2nm, under the RibbonFET moniker for 20A (20 angstroms equals 2nm)

What comes after that likely will be complementary FETs (CFETs). TSMC plans to introduce CFETs at some point after 2nm. Imec, meanwhile, has developed a way to extend nanosheets by at least a node through stacked nanosheets and forksheet FETs. CFETs are on Imec’s logic technology roadmap beyond 1nm. Imec is researching two different integration schemes for fabricating CFETs, monolithic and sequential.

Fig. 1: N and P-type forksheet FET (left) and stacked nanosheet FET (right). Source: Imec

After that, it appears no one knows exactly what future transistors will look like. Yuh Jier Mii, TSMC’s senior vice president of R&D, identified 2D transition metal dichalcogenides (TMDs) and carbon nanotube FETs as possible candidates. He also said new materials such as bismuth and antimony may be required for 2D transistor contacts, along with air gapping to control capacitance.

There are a number of other technologies that need to be developed along the way, as well, such as how to get power into these transistors when they are so densely packed, and how to move more data much more quickly without burning up these chips or packages. These issues become more pronounced at each new node, and potentially more expensive to solve.

Two main power delivery approaches have emerged. One is backside power delivery. The other is buried power rails. Imec demonstrated a scheme that uses both. “We believe that combining backside power delivery with buried power rails – a structural scaling booster in the form of a local power rail that is buried deep in the chip’s front-end-of-line – is the most promising implementation scheme of a backside power delivery network in terms of scalability and performance,” said Naoto Horiguchi, Imec’s director of CMOS device technology.

How far this roadmap ultimately will go remains uncertain. But leading-edge foundries are taking a multi-pronged approach, betting on advanced packaging approaches that can accommodate multiple chips or chiplets developed at different process nodes, including these new devices. Industry insiders said the current thinking is that overall costs may be more manageable with heterogeneous integration and a standardized interconnect approach between chips or chiplets.

Fig. 2: TSMC’s multi-pronged strategy includes a variety of advanced packaging options. Source: TSMC

Acquisitions and Money
Applied Materials acquired Picosun Oy, a privately held Finnish company specializing in atomic layer deposition (ALD) technology. Financial terms were not disclosed and no further approvals are required.

Patience continues to wear thin in the chip industry, and with the U.S. Congress due to take their seasonable August recess, the heat is on. Chief executives from Intel, GF, Onto Innovation, Amkor, TEL, Nvidia, TI, and 116 other leaders signed a letter urging the U.S. House of Representatives and Senate to set aside differences in the bills each has passed and send one bill to President Joe Biden for signature.

“Our global competitors are investing in their industry, their workers, and their economies, and it is imperative that Congress act to enhance U.S. competitiveness,” said the letter, organized by the SIA. Legislation includes $52 billion in federal funding under the Chips Act to increase U.S. semiconductor fab capacity. What’s at stake? The U.S. share of semi manufacturing capacity has decreased from 37% in 1990 to 12% today, primarily due heavy government subsidies in other countries.

Fab Equipment
Global fab equipment spending for front-end facilities is expected to reach an all-time high of US$109 billion in 2022, a growth of 20% versus 2021, according to the recent SEMI report.

Fig. 3: Fab Equipment Spending Source: SEMI

MCUs and Automotive Chips
2021 MCU sales reached a record-high of $20.2 billion, a 27% year-over-year growth, strongly driven by embedded automation and increased sensors. 82% of 2021 MCU sales came from 5 suppliers, including NXP, Microchip, Renesas, ST and Infineon, according to IC Insights.

In response to market demand for higher MCU performance, Renesas announced development of circuit technologies for an embedded spin-transfer torque magnetoresistive random-access memory (STT-MRAM, hereinafter MRAM) test chip with fast read and write operations fabricated using a 22nm process. The test chip includes a 32-megabit embedded MRAM array, with 5.9-ns random read access at a maximum junction temperature of 150°C, and a write throughput of 5.8 MB/s.

Given the chip shortage will likely extend into 2023, Mckinsey points to a number of solutions and long-term demand planning to aid the automotive sector through the semiconductor crisis, including “OEMs and suppliers could build a long-term perspective on demand. This will allow them to consider jointly investing in projects involving mature nodes. Alternatively, both groups may codevelop semiconductors in advanced or leading-edge nodes. These strategies will allow them to share the financial burden while improving the supply of low-margin or highly innovative technologies.”

Materials, GAA & Quantum
Argonne National Lab created a new AI tool that will aid in materials discovery. The new tool, inspired by the popular AlphaGo game, features a reinforcement learning algorithm to model the properties of materials at the atomic and molecular scale.

A new research paper from IBM’s T.J. Watson Research Center and Brookhaven National Laboratory describes a “synchrotron x-ray diffraction-based non-destructive nanoscale mapping of Si/SiGe nanosheets for gate-all-around structures.”

CEA-Leti and others presented “Specificities of FDSOI QD Arrays Integration and Characterization” at the 2022 IEEE VLSI Symposium on Technology & Circuits this week. The research includes a “three-step characterization chain for linear silicon quantum dot (QD) arrays fabricated on fully depleted silicon-on-insulator (FDSOI) material. “

Deals and certifications
TSMC certified Synopsysdigital and custom design flows for its N3E and N4P process technologies. In addition, Synopsys’ Foundation IP and Interface IP are available on the TSMC N3E and N4P processes to accelerate SoC development and minimize design risk.

Fig. 4: TSMC’s different node options. Source: TSMC

SK Hynix selected Lam Research’s dry resist fabrication technology for two key process steps to produce advanced DRAM chips. The dry resist technology extends the resolution, productivity, and yield of EUV lithography.

TSMC certified Siemens’ Aprisa digital implementation solution for its N5 and N4 advanced process technologies.

The European General Court ruled against an approximately $1 billion fine imposed on Qualcomm by EU antitrust regulators in 2018. The original case argued that Qualcomm paid billions to Apple from 2011 to 2016 to only use its chips in its IPads and iPhones in order to block out rivals.

Further Reading
June’s Manufacturing, Packaging and Materials newsletter published this week includes these new featured stories, along with many blogs and white papers:

  • Ways To Address The Materials Crunch
  • Variation Making Trouble In Advanced Packages
  • High-NA EUV May Be Closer Than It Appears

Semiconductor Engineering’s latest Test, Measurement & Analytics newsletter is here, including a special report on keeping IC packages cool. Other top stories include getting to zero defects in auto ICs, removing barriers for end-to-end analytics, and deep learning in inspection.

Chip Industry Business News & Startups
Semiconductor Engineering has launched its new Business & Startups page. Find the latest chip industry stock chart, monthly detailed startup funding reports (including a deep-dive into China’s startups), profiles of new startups, as well as the latest business news.

Upcoming Events
Find upcoming chip industry events, including:

  • Frontiers of Characterization & Metrology for Nanoelectronics (FCMN): June 20-23 (Monterey, CA)
  • International Interconnect Technology Conference (IITC): June 27-30 (San Jose, CA/Hybrid)
  • Semicon West/DAC: July 11-14 (San Francisco & virtual)

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