Integrating vdW-Interface-Based high-κ Dielectrics On Both n- And p-Type 2D Semiconductors (Sungkyunkwan U., KAIST)


A new technical paper "High-κ dielectric van der Waals integration on 2D semiconductors for three-dimensional complementary logic systems" was published by researchers at Sungkyunkwan University and KAIST. "This scalable methodology enables the vertical integration of complementary logic, demonstrated by complementary FET inverters and ring oscillators, establishing a promising route toward... » read more

Understanding CFETs, A Next Generation Transistor Architecture


Computing power has experienced exponential growth over the last 70 years. This has largely been achieved through transistor scaling. Due to a continuous reduction in the size of transistors, engineers have been able to pack more and more of them onto a single chip [1]. This has led to faster, more powerful, and more energy-efficient devices. Improvements in fabrication processes and materials,... » read more

Week In Review: Manufacturing, Test


Node scaling wars are revving up, although much of the action is happening where most people can't see it — inside of research labs. This is difficult stuff, which makes delivery dates difficult to pinpoint, and no one wants to give away their competitive position or commit to a timeline they can't keep. Billions of dollars of leading-edge research — funded by pure-play foundry TSMC, IDM... » read more