Manufacturing Bits: July 14

3D complementary FETs; 2D MoS2 FETs.


Complementary FETs
At the recent 2020 Symposia on VLSI Technology and Circuits, Imec presented a paper on a 3D complementary field-effect transistor (CFET) made on 300mm wafers.

As a demonstration vehicle, Imec showed a CFET based on a 14nm process. Ideally, though, CFETs are next-generation transistors that are targeted for the 1nm node in the future.

On the transistor front, chipmakers are currently shipping finFET transistors, which will extend to the 3nm and/or 2nm foundry node. Then, at 3nm or 2nm, chipmakers are expected to migrate to a gate-all-around transistor. The nanosheet FET, one gate-all-around type, is the gaining steam. A nanosheet FET is a finFET on its side with a gate wrapped around it.

The nanosheet FET could extend beyond 2nm. Other options are in the works. “As we approach the limits of scaling, novel device architectures are needed in order to meet the demand of a smaller transistor footprint while maintaining a high performance. For nodes beyond the 5nm regime, several options have been proposed. The most promising of these ideas include vertically stacked nanosheets, forksheets, and CFETs,” said Sujith Subramanian, an R&D engineer at Imec and lead author of the paper. Others contributed to the work.

Typically, gate-all-around FETs use different devices for the nFETs and pFETs. The CFET is appealing for several reasons. “A CFET architecture, where NMOS and PMOS devices are vertically stacked and are controlled using a common gate, would result in a maximum device footprint reduction,” Subramanian said.

For this work, Imec used a monolithic CFET process, compared to a sequential process. “In this work, for the first time, we demonstrate PMOS finFET bottom devices and NMOS nanosheet top devices on 300mm wafers using a CFET fabrication process. Due to a smaller N/P separation, monolithic CFETs have lower parasitic resistances (REFF) and capacitances (CEFF) compared to sequential CFETs, which results in higher performance gains. Moreover, wafer cost of a monolithic CFET process would be lower than that of a sequential CFET,” Subramanian said.

In this work, the transfer characteristics of the bottom pMOS finFET at drain voltage was VD= -0.8V. The top NMOS nanosheet FET was at VD= 0.8V. Both devices had 8 fins with a 20nm gate length.

2D materials are also gaining steam in the R&D labs. In 2004, graphene was the first 2D material isolated. Other 2D materials include boron nitride and the transition-metal dichalcogenides (TMDs).

One TMD, molybdenum diselenide (MoS2), is gaining interest in the market. This 2D materials could enable a new class of field-effect transistors (FETs), but the technology isn’t expected to appear for some time.

According to Imec’s roadmap, a CFET with 2D channel materials could appear at the sub-1nm node. At the 2020 Symposia on VLSI Technology and Circuits, TSMC, MIT, National Taiwan University and the National Chiao Tung University presented a paper on an MoS2 FET.

MoS2 FETs have good mobility with a moderate energy bandgap and low off-state currents. The challenge is to grow MoS2 monolayers using chemical vapor deposition (CVD). Making low resistance metal contact are also essential for achieving drive current.

“We demonstrate the highest nFET current of 390 A/m at VDS = 1 V based on CVD MoS2 monolayers without intentional doping. The transistor exhibits good subthreshold swing of 109 mV/decade, large ION/IOFF ratio of 4 x 108, and nearly zero DIBL. The high on-current achieved in monolayer MoS2 nFET is mainly attributed to the thin EOT ~2 nm of HfOx gate oxide, short gate length of 100 nm, and low contact resistance ~1.1 k-m,” according to Ang-Sheng Chou from TSMC and Jing Kong from MIT in the paper.

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