Wafer-on-Wafer Hybrid Bonding: Reticle Placements To Achieve Efficient NW Topologies (ETH Zurich)


Researchers from ETH Zurich published the new technical paper "Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding." Abstract "Transformer-based large language models are increasingly constrained by data movement as communication bandwidth drops sharply beyond the chip boundary. Wafer-scale integration using wafer-on-wafer hybrid bonding alleviates this limitation by p... » read more

Full Wafer Integration of Aggressively Scaled 2D-Based Logic Circuits (Imec)


A technical paper titled "Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits" was published by researchers at Imec. "The introduction of highly scaled 2D-based circuits for high-performance logic applications in production is projected to be implemented after the Si-sheet-based CFET devices. Here, a view on the requirements needed for full waf... » read more