What’s Next In Advanced Packaging?

By Ed Sperling And Laura Peters - 19 Feb, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC progress and issues, photonics, and tradeoffs with different interposers and bridge technologies, with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What fo... » read more

FOWLP Warpage: Review Of Causes, Modeling And Methodologies For Controlling

By Technical Paper Link - 14 Feb, 2025 - Comments: 0

A new technical paper titled "Warpage in wafer-level packaging: a review of causes, modelling, and mitigation strategies" was published by researchers at Arizona State University. Abstract "Wafer-level packaging (WLP) is a pivotal semiconductor packaging technology that enables heterogeneously integrated advanced semiconductor packages with high-density electrical interconnections through i... » read more

Navigating Increased Complexity In Advanced Packaging

By Gregory Haley - 17 Dec, 2024 - Comments: 1

As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

Emerging Technologies Driving Heterogeneous Integration

By Ed Sperling - 24 Sep, 2024 - Comments: 0

As chips are disaggregated into chiplets, more features are being added into these devices that chipmakers were unable to include in the past due to reticle size limits and the high cost of scaling everything to the latest process node. This has opened the door to new architectures, new materials such as glass substrates, and a variety of new challenges. Dick Otte, president and CEO of Promex I... » read more

Precision Patterning Options Emerge For Advanced Packaging

By Gregory Haley - 23 Jul, 2024 - Comments: 0

The chip industry is ratcheting up investments in advanced packaging as it strives to keep pace with demands for increased functionality and higher performance, including novel patterning technologies that can reduce costs and speed time to market. Success in advanced packages is partly dependent on effectively managing the interconnectivity between the chips, which requires increasingly pre... » read more

Thermal Challenges Multiply In Automotive, Embedded Devices

By Karen Heyman - 02 Jul, 2024 - Comments: 0

Embedding chips into stacked-die assemblies is creating thermal dissipation challenges that can reduce the reliability and lifespan of these devices, a growing problem as chipmakers begin cramming chiplets into advanced packages with thinner substrates between them. In the past, nearly all of these complex designs were used in tightly controlled environments, such as a large data center, whe... » read more

Controlling Warpage In Advanced Packages

By Laura Peters - 24 Jun, 2024 - Comments: 1

Warpage is becoming a serious concern in advanced packaging, where a heterogeneous mix of materials can cause uneven stress points during assembly and packaging, and under real workloads in the field. Warpage plays a critical role in determining whether an advanced package can be assembled successfully and meet long-term reliability targets. New advances, such as molding compounds with impro... » read more

Overlay Optimization In Advanced IC Substrates

By Ed Sperling - 29 Apr, 2024 - Comments: 1

Overlay is becoming a significant problem in the manufacturing of semiconductors, especially in the world of advanced packaging substrates — think panels — the larger the area, the greater the potential for distortion due to warpage. Solving this issue requires more accurate models, better communication through feed forward/feed back throughout the flow, and real-time analytics that are bak... » read more

Challenges With Chiplets And Power Delivery

By Ed Sperling - 15 Apr, 2024 - Comments: 0

Chiplets hold the potential to deliver the same PPA benefits as an SoC, but with many more features and options that are possible on a reticle-constrained die. If chiplets live up to the hype, they will deliver what is essentially mass customization, democratizing and speeding the delivery of complex chips across a broad array of markets. Today, the focus has been on die-to-die interfaces, but ... » read more

Predicting Warpage in Different Types of IC Stacks At Early Stage Of Package Design

By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects" was published by researchers at Siemens EDA, D2S, and Univ. Grenoble Alpes, CEA, Leti. Abstract: "A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The ... » read more

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