DAC System Design Contest


When it comes to tackling leading-edge design challenges in fun ways, there’s no better place than DAC. For DAC 2018, we’ve created a System Design Contest targeting machine learning on embedded hardware. If you think this is too leading edge for a design contest, you’d be mistaken: More than 100 teams registered for the contest. You can find a full list of the teams here. So ho... » read more

Using FPGAs For Emulation


For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover some of the time lost on RTL simulation. Meanwhile, FPGA technology has been available long enough to mature to the point where FPGA bas... » read more

Prototyping Partitioning Problems


Gaps are widening in the prototyping of large, complex chips because the speed and capacity of the FPGA is not keeping pace with rapid rollout pace of advanced ASICs. This is a new twist for a well-established market. Indeed, prototyping with FPGAs is as old as the [gettech id="31071" t_name="FPGAs"] themselves. Even before they were called FPGAs, logic accelerators or LCAs (logic cell ar... » read more

The Week in Review: IoT


Security Mocana said it is working with Avnet, Infineon Technologies, Microsoft, and Xilinx to provide Industrial Internet of Things systems that meet cybersecurity standards. The systems utilize the Avnet UltraZed-EG system-on-module, Mocana’s security software running on the Xilinx Zynq Ultrascale+ MPSoc, and Infineon’s OPTIGA Trusted Platform Module 2.0 security chip. The Microsoft Azur... » read more

The Week in Review: IoT


Finance Automile, an Internet of Things company involved in field-service businesses, has received $34 million in Series B funding led by Insight Venture Partners, bringing its total funding to $47 million. Existing investors Dawn Capital, Point Nine Capital, SaaStr Fund, and Salesforce Ventures also participated in the new round. Automile will use the money on marketing, product developmen... » read more

The Week In Review: Design


Tools Cadence unveiled a new equivalence checking tool which features a massively parallel architecture capable of scaling to 100s of CPUs and adaptive proof technology that analyzes each partition and determines the optimal formal algorithm. According to the company, the Conformal Smart Logic Equivalence Checker provides an average of 4X runtime improvement with the same resources over the pr... » read more

A Chip For All Seasons


FPGAs are showing up in more designs and in more markets, and as they get included in more systems they are becoming much more complex. A decade ago, the key markets for [gettech id="31071" t_name="FPGAs"] were industrial, medical, automotive and aerospace. Those markets remain strong, but FPGAs also are playing a role in artificial intelligence, data centers, the [getkc id="76" kc_name="... » read more

The Week In Review: Design


M&A Invecas will acquire Lattice Semiconductor's HDMI design team and Simplay Labs subsidiary, which oversees standards compliance and interoperability testing services. Invecas supplies foundation, analog, and interface IP optimized for GlobalFoundries processes. The deal is expected to close later this month. Last year, Lattice announced it would be acquired by Chinese private equity fir... » read more

CCIX Enables Machine Learning


It takes a lot of technology to enable something like machine learning, and not all of it is as glamorous as neural network architectures and algorithms. Several levels below that is the actual hardware on which these run, and that brings us into the even less sexy world of interfaces. One such interface, the Cache Coherent Interconnect for Accelerators (CCIX), pronounced C6, aims to make th... » read more

The Week In Review: Design


IP Synopsys unveiled High Bandwidth Memory 2 (HBM2) IP. The package includes PHY, controller and verification IP and supports data rates up to 2400Mb/s, 20% faster than the JEDEC standard specification. The controller supports pseudo-channel operation in either lock step or memory interleaved mode, and the PHY offers four trained power management states and fast frequency switching. Cadence... » read more

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