Achieving Separation On Multiprocessor SoCs For Enhanced Safety And Security

By Dan Driscoll - 27 Jul, 2017 - Comments: 0

As I read my colleague Andrew Caples’ article on The Blurring of Safety and Security for Embedded Devices, I immediately started to think of the Xilinx UltraScale+ MPSoC – as I have engaged with numerous customers about using this chip for both safety and security purposes, and the requirements for both areas are definitely starting to blur. I quickly realized a blog about the Xilinx... » read more

Blog Review: July 26

By Jesse Allen - 26 Jul, 2017 - Comments: 1

Mentor's Dan Driscoll digs into designing for safety and security on the Xilinx UltraScale+ MPSoC and the different mechanisms that support subsystem isolation. Cadence's Paul McLellan listens in on a talk by Bosch's Volkmar Denner on the future of communications and AI in connected autos. Synopsys' Robert Vamosi points to a recently-discovered vulnerability that could be present in thous... » read more

The Week In Review: Design

By Jesse Allen - 14 Jul, 2017 - Comments: 0

M&A Ansys acquired Computational Engineering International (CEI), the developer of a suite of products that helps analyze, visualize and communicate simulation data. Founded in 1994 as a spin-off from Cray Research, the company's program covers a wide range of data formats. Terms of the deal were not disclosed. IP Efabless launched an open source framework that allows community members... » read more

Shrink Or Package?

By Ed Sperling - 19 Jun, 2017 - Comments: 0

Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

The Week In Review: IoT

By Jeff Dorsch - 16 Jun, 2017 - Comments: 0

Market Research International Data Corp. updated its Worldwide Semiannual Internet of Things Spending Guide, forecasting global IoT spending will increase 16.7% this year to more than $800 billion. The market research firm says the market will grow to almost $1.4 trillion by 2021. Manufacturing, smart grid technologies, freight monitoring, production asset management, and smart building techno... » read more

Security Issues Up With Heterogeneity

By Ann Mutschler - 05 Jun, 2017 - Comments: 0

The race toward heterogeneous designs is raising new security concerns across the semiconductor supply chain. There is more IP to track, more potential for unexpected interactions, and many more ways to steal data or IP. Security is a difficult problem no matter what kind of chip is involved, and it has been getting worse as more devices, machines and systems are connected to the Internet. B... » read more

It’s Show Time

By Henry Chan - 25 May, 2017 - Comments: 0

It’s been a busy season. The weather has warmed here in the desert and as the trees and greenery enliven in spring, The whole industry is bursting with activity. From DVCon to the International Symposium on FPGAs in the United States to Embedded World and CTIC in Europe, there have been a number of important developments in verification, embedded systems, and DO-254. The DVCon U.S. Confere... » read more

Whatever Happened To HLS?

By Brian Bailey - 24 May, 2017 - Comments: 1

A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high-lev... » read more

Speeding Up Neural Networks

By Ed Sperling - 27 Apr, 2017 - Comments: 2

Neural networking is gaining traction as the best way of collecting and moving critical data from the physical world and processing it in the digital world. Now the question is how to speed up this whole process. But it isn't a straightforward engineering challenge. Neural networking itself is in a state of almost constant flux and development, which makes it something of a moving target. Th... » read more

Software Driven Test Of FPGA Prototype

By Krzysztof Szczur - 27 Apr, 2017 - Comments: 0

Most everyone would agree how important FPGA prototyping is to test and validate an IP, sub-system, or a complete SoC design. Before the design is taped-out it can be validated at speeds near real operating conditions with physical peripherals and devices connected to it instead of simulation models. At the same time, these designs are not purely hardware, but these days incorporate a significa... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: Xilinx