Tailoring IP, Tools And Flows

Complexity and software content will force changes in the IP and flows for specific applications.


By Ann Steffora Mutschler
As SoC and system complexity rises continually and software drives much more in a system, specific vertical application areas will require tailored IP and tool flows to allow designers to meet time-to-market demands.

Today, many systems are designed around a platform, which contains most of the STAR IP—processors, GPUs, memory controllers, interconnects, memory subsystem, etc.—on the platform either fixed or with a defined migration path for these IP, said Nitin Chawla, chief scientist for Mentor’s Catapult C team.

“Where we look at a place for active differentiation is adding or redefining the application engines, such as wireless modems, video processing pipelines, encoding/decoding/transcoding engines. These are things that would keep your platform scalable for most of the software content but also add additional functionality to differentiate your product,” he said.

The big challenge for the digital consumer market, which is where many of these SoCs either directly or indirectly play, is to maintain or improve design productivity given the shorter time to market window. Another challenge is getting good quality results because most of these blocks have limited reconfigurability, so they need to be extremely low in terms of their cost to area and power, he said.

“Given the fact that you can do a lot of design exploration and choose an architecture that is best suited for that specific technology node and performance requirements—this is a design need. The idea is to be able to support this design need without disrupting the conventional implementation that is RTL to GDSII,” Chawla added.

However, continuing on the path of taking the horizontal, more baseline flows and just adding some capabilities to make them more applicable toward specific applications or verticals—basically the way EDA has done things in the past—is not scaling any longer, said Michal Siwinski, senior director of solution and product marketing at Cadence.

“With software taking a more important role in differentiation of the end offering, at the end of day having silicon that is 1% smaller or slightly faster in most applications on the market is no longer the primary criteria. Clearly, for some specialized applications that’s still the key factor but what is becoming differentiating is shifting. The more that shifts, the more the trend is to a top-down, vertical approach being necessary to the way the tools and solutions are being developed and deployed.”

“If you really take a clean slate and think about what is needed to enable a mobile market, or to enable what is needed in networking, or storage for example, from a top down perspective the requirements are so fundamentally different than starting from a clean slate – a lot of the underlying technologies that you would then build to support that would be drastically different,” Siwinski explained.

Vertical-specific IP ahead?
When it comes to narrowly-focused applications, Vishal Kapoor, VP of marketing for SoC realization at Cadence, does not believe it makes sense from a business perspective to have 100% vertical-specific IP. Cadence is making a bet that with convergence, there is a very significant demand on the memory interfaces.

“If you look at our DDR controller, we’ve got DDR controllers going in from consumer devices all the way to supercomputers,” said Kapoor. “The reason we are able to do that is if you take IP and make it very vertical-specific, you’re narrowing the market; but if you make it very configurable so that you can deliver specific configurations to your customers, that makes sense.”

Based on his experience on the graphics and wireless side of things, Arteris director of marketing Kurt Shuler explained that the tools needed to create the test load or the software that runs on it are different in those areas. Also, how success or failure is measured is different, as are the metrics.

“If you’re doing a big graphics chip that’s running in a PC it’s very different than something that’s going to be running in a cell phone. So the infrastructure behind that is different. The tools and the players are different. If you are doing something on the wireless side, they can get really complicated because if you back up all the way, they have to get these things certified that work under different cellular networks,” he said.

Further, the IP must be configurable to every SoC so that when the designers are putting the SoC together, it allows for architectural exploration since every customer asks for power, performance, gate count, noted Frank Ferro, director of marketing at Sonics.

Of course, application-specific IP exists today, mainly in the form of subsystems, noted Prasad Subramaniam, vice president of design technology at eSilicon. Chip designers are beginning to take the building block approach to the next level in creating subsystems that are targeted to specific applications by combining different pieces of IP together in the most common way that they would be used. Then they leave the rest to the imagination of the end customer to customize their own proprietary know-how so that it is easier for them to build their end application, he explained.

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