TCAD Simulation Challenges For Gate-All-Around Transistors

By Victor Moroz and Shela Aboud

The transition from finFET technology to Gate-All-Around (GAA) technology helps to reduce transistor variability and resume channel length scaling. It also brings several new challenges in terms of transistor design that need to be addressed.

One of the challenges is handling the thin Si layers that come with GAA technology, where Si channel thickness scales down to ~4nm, as opposed to ~5.5nm that was typical for finFET technology. Such a thin channel is necessary to suppress short channel effects and enable channel length scaling. One of the side effects of going below ~5 nm Si thickness is that the Si bulk band structure is not valid anymore, and to accurately model the GAA transistors it is necessary to use sub-band Boltzmann transport, as illustrated in figure 1.

Fig. 1: Difference in Idlin and Idsat GAA currents between Boltzmann transport with Si bulk bandstructure (Garand Monte Carlo) and Boltzmann with sub-bands (Sentaurus Device QTX SBTE).

Another key side effect of the thinner channel is that the valence band edge energy Vb goes down by >100 mV (figure 2). The implications of that energy shift are that it becomes more difficult to manufacture PMOS transistors with low Vt that is necessary for HPC (high performance computing). This effect is compounded by the reduced stress in GAA PMOS transistors with respect to PMOS FinFETs, which further pushes the Vb down.

Fig. 2: Valence band DOS for different channel thicknesses and different channel materials based on ab-initio analysis in Quantum ATK.

Yet another important side effect of the Vb lowering on PMOS GAA behavior is the increased NBTI (Negative Bias Temperature Instability) transistor aging. To mitigate this negative impact on PMOS GAA behavior with respect to finFETs there is an effort to bring Ge into the PMOS GAA channel. One way to do it is by growing an epitaxial “cladding” SiGe layer on top of the Si core (figure 3).

Fig. 3: Cross-section of PMOS GAA transistor channel with Si core and SiGe cladding layer. The current is going into the screen (if you are looking at this on a screen).

Atomistic view of such structures shows considerable randomness in the Ge locations due to the relatively low Ge content of ~25% (figure 4).

Fig. 4: Valence band DOS map for a Si GAA channel with 25% SiGe cladding, obtained in Quantum ATK. The Ge atoms elevate Vb energy, indicated by the red shift on this color map.

Ab-initio analysis of such structures shows a bumpy Vb surface, with Vb energy peaks happening around higher Ge content (figure 5).

Fig. 5: Valence band landscape for the PMOS GAA channel with Si core and 25% SiGe cladding obtained by ab-initio analysis in Quantum ATK.

The impact of the channel thickness on valence band along with the impact of channel composition, including Si, Si core with SiGe cladding, and all-SiGe can be seen in figure 2. Ab-initio analysis of such structures in Quantum ATK combined with advanced transport in Sub-band Boltzman-based analysis enables fine-tuning of the GAA transistor behavior in terms of its performance, Vt engineering, and reliability engineering.

Synopsys TCAD tools are well suited to address the simulation challenges of GAA technology.  Utilizing fundamental atomic simulations of QuantumATK, a new Sentaurus Advanced Transport package for semi-classical transport enables the design and optimization of the next generation of logic transistors based on GAA technology.

The Sentaurus Advanced Transport Tool from Synopsys offers significant benefits for simulating state-of-the-art logic devices, particularly as technology advances towards more complex nodes such as Gate-All-Around (GAA) transistors. As devices scale down, traditional TCAD tools face challenges due to quantum effects and short channel mobility in these scaled channel geometries. The Sentaurus Advanced Transport Tool addresses these challenges by integrating advanced physics and simulation methodologies capable of capturing the intricate behaviors of electrons in small channels. This tool is essential for modeling the quantum effects that become prominent in nanoscale devices, ensuring accurate simulation of GAA and CFET (Complementary FET) structures. Additionally, the tool supports the evaluation of new materials in the gate stack and interconnect technology, making it a comprehensive solution for modern semiconductor device design. Overall, the Sentaurus Advanced Transport Tool is pivotal in advancing the simulation capabilities needed to innovate and optimize next-generation semiconductor devices.

Shela Aboud is a senior staff technical product manager in the EDA Group at Synopsys.