Detect RDC issues in highly complex reset architectures
Modern SoCs are equipped with complex reset architectures to meet the requirements of high-speed interfaces with increased functionality. These complex reset architectures with multiple reset domains, ensure functional recovery from hardware failures and unexpected electronic faults. But the transmission of data across sequential elements that are reset by different asynchronous and soft reset domains can cause reset domain crossing (RDC) paths, which can lead to metastability. This metastability can cause unpredictable values to be propagated to down-stream logic and prevent a design from functioning normally. A proper reset domain crossing sign-off methodology is required to avoid metastability and other functional problems in chip designs. This paper presents a systematic methodology, as a part of static analysis, to intelligently identify critical reset domain bugs associated with soft resets. A soft reset is a mechanism that initiates a controlled reset within the system without fully powering it off.
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