How to reduce defect levels by targeting specific faults.
Tessent Cell-Aware ATPG is a transistor-level ATPG-based test methodology that achieves significant quality and efficiency improvements by directly targeting specific shorts; opens and transistor defects internal to each standard cell; resulting in significant reductions in defect (DPM) levels. Traditional scan patterns are created using fault models that are based on the logical operation of the library cells. However, there are defects that can occur within the library cells that are not ensured to be detected with traditional patterns and fault models. This is even more significant an issue with newer technologies where the defect locations are occurring more and more inside the cells and some cell designs are becoming more complex. As a result, cell-aware test was introduced to determine the location of defects within the library cells and produce test patterns that ensure detection of those defects. Silicon results show that cell-aware test is able to detect more than 800 defects per million even after exhaustive stuck-at and transition patterns are performed.
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