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Tessent Cell-Aware Test


Tessent Cell-Aware ATPG is a transistor-level ATPG-based test methodology that achieves significant quality and efficiency improvements by directly targeting specific shorts; opens and transistor defects internal to each standard cell; resulting in significant reductions in defect (DPM) levels. Traditional scan patterns are created using fault models that are based on the logical operation of t... » read more

Transistor-Level Defect Diagnosis


Each new semiconductor process node represents exciting opportunities for suppliers of design, manufacturing, test, and failure analysis solutions. A new process means new challenges to solve, and hopefully more money to be made. On the flip side, whenever solutions that address these new challenges are presented, we seldom hear how useful these are to more mature process nodes. One technology ... » read more