How to improve performance and optimize data throughput in multicore architectures.
AI chips, regardless of the application, are not regular ASICs and tend to be very large, this essentially means that AI chips are reaching the reticle limits in-terms of their size. They are also usually dominated by an array of regular structures and this helps to mitigate yield issues by building in tolerance to defect density due to the sheer number of processor blocks.
The reason behind the large die size allows AI chip designers to implement multiple, repeated processor cores. Moortec provides IP that can be integrated into the array and between the cores. Some companies are starting to experiment with different layout scenarios, such as placing certain blocks within the pad rings or within specific routing channels within the chip.
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