AI Accelerator Testing Depends On DFT Innovations

By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

Building an AI Chip: Security, Software Development, and Lifecycle Management

By Synopsys - 25 Mar, 2026 - Comments: 0

The third white paper in our series, "Building an AI Chip" delves into the critical aspects of ensuring robust security and efficient software development for AI chips. As AI applications become increasingly integrated into everyday systems, the need for secure and reliable chip designs is paramount. This paper outlines essential strategies for safeguarding AI chip development, optimizing softw... » read more

Adaptive Test Gaining Ground For HPC And AI Chips

By Gregory Haley - 09 Dec, 2025 - Comments: 0

Adaptive test is starting to gain traction for high-performance computing and AI chips as test programs that rely on static limits and fixed test sequences reach their practical limits. The growing complexity of multi-die assemblies and power delivery, along with increased stresses, are forcing a shift toward real-time, data-driven optimization at the test cell. “It’s the same old pro... » read more

MIT’s Survey On Accelerators and Processors for Inference, With Peak Performance And Power Comparisons

By Technical Paper Link - 31 Oct, 2025 - Comments: 0

A new technical paper titled "Lincoln AI Computing Survey (LAICS) and Trends" was published by researchers at MIT Lincoln Laboratory Supercomputing Center. Abstract "In the past year, generative AI (GenAI) models have received a tremendous amount of attention, which in turn has increased attention to computing systems for training and inference for GenAI. Hence, an update to this survey is ... » read more

Multi-Die Verification

By Ed Sperling - 13 Oct, 2025 - Comments: 1

Chiplets offer unprecedented flexibility in high-performance designs, but they also add new challenges on the verification side. Changing out a chiplet, or adding a new one, can mean having to re-verify an entire multi-die system, a problem that becomes even more complicated if those chiplets are developed by different vendors. Paul Graykowski, director of product marketing at Cadence Design Sy... » read more

The Criticality of Performance per Watt Optimization for AI Chip Development

By Synopsys - 03 Sep, 2025 - Comments: 0

Chip developers are seeing an urgent rise in demand for compute processing capability driven by AI workloads. This increase in compute requirements drives a corresponding increase in the demand for power consumption. For example, a ChatGPT query requires nearly 10 times as much power, on average, as a Google search. Power has traditionally been treated as a secondary constraint, with perform... » read more

DL Compiler Framework For More Efficient Inter-Core Connected AI Chips (UIUC, Microsoft)

By Technical Paper Link - 21 Jul, 2025 - Comments: 0

A new technical paper titled "Elk: Exploring the Efficiency of Inter-Core Connected AI Chips with Deep Learning Compiler Techniques" was published by researchers at the University of Illinois Urbana-Champaign (UIUC) and Microsoft Research. Abstract "To meet the increasing demand of deep learning (DL) models, AI chips are employing both off-chip memory (e.g., HBM) and highbandwidth low-laten... » read more

Mastering AI Chip Complexity: Your Guide to First-Pass Silicon Success

By Synopsys - 28 May, 2025 - Comments: 0

This eBook provides a resource for innovators in the fast-changing realm of AI chip development. It delves into the opportunities and challenges of designing cutting-edge AI chips and chiplets, focusing on the transition from traditional monolithic architectures to multi-die and chiplet-based solutions. The content covers essential topics such as architectural exploration, silicon design, a... » read more

Problems In Testing AI Chips

By Ed Sperling - 20 May, 2025 - Comments: 0

As AI chips get larger, it becomes much harder to test them. Today, there can be as many as 22,000 pins on a 150mm² die, but in the future that number may increase to 80,000 pins. That creates a huge challenge for the fabs and the testers. Jack Lewis, chief technologist at Modus Test, talks about the intricacies of testing these complex devices, from maintaining contact with those pins even on... » read more

New Approaches To Power Decoupling

By Bryon Moyer - 24 Oct, 2024 - Comments: 0

Decoupling capacitors have long been an important aspect of maintaining a clean power source for integrated circuits, but with noise caused by rising clock frequencies, multiple power domains, and various types of advanced packaging, new approaches are needed. Power is a much more important factor than it used to be, especially in the era of AI. “Doing an AI search consumes 10X the power t... » read more

← Older posts

tag: AI chips