Meeting all the testability analysis required by ISO 26262.
For as long as semiconductor devices have been around, motor vehicles have been one of the toughest operating environments. Chips in automobiles, trucks, and buses are subject to extremes of temperature, humidity, vibration, and radiation. The challenges of designing for these environmental conditions have grown more pronounced with advanced technology nodes, which are necessary to satisfy market requirements. This post looks at how to test automotive chips, both in production and in the field, to ensure that they will perform as intended.
In just the last few years, the chips in motor vehicles have become some of the largest and most complex in the semiconductor industry. Advanced driver assistance systems (ADAS) must integrate a wide range of sensor data and analyze it in real time. AI is increasingly used, and it is the basis for the emerging autonomous vehicle market. Chips that control essential driving functions must not fail due to manufacturing defects. Manufacturing test must achieve a very low rate of less than one defective part per million (DPPM).
Automotive chips also must not fail due to faults caused by the challenging environment or silicon aging. Faults must be detected and handled gracefully in the field, even as vehicles are driving at high rates of speed, by on-chip self-test systems. The built-in self-test (BIST) solution must encompass both logic (LBIST) and memory (MBIST). Given the computational demands of AI and the competitive nature of the automotive market, the testing systems must have minimal impact on chip power, performance, and area (PPA).
Automotive chips must satisfy multiple industry standards, including ISO 26262 for functional safety (FuSa). Safety mechanisms such as error correcting codes (ECCs) and triple modular redundancy (TMR) are generally needed in the chip to help detect in-field faults. All test logic must work reliably even under the harshest environmental conditions, including detecting faults in its own functionality. Software FuSa support also plays a role by ensuring that a non-recoverable fault, once detected, results in the vehicle being brought to a stop in a safe location.
A complete test solution for automotive chips has many elements, some of which are mandated by ISO 26262. For example, this standard defines the Single Point Fault Metric (SPFM) and requires calculations of this metric. Satisfying the standard also requires static functional safety analysis on either the register transfer level (RTL) design or the gate-level netlist, and this analysis must be fast to minimize the impact on the chip project schedule. The results may lead to design changes to improve functional safety and comply with the standard.
The standard also mandates high-quality fault simulation with a very high chance of catching manufacturing defects. In addition to fast simulation, this requires advanced fault models well beyond the traditional single stuck-at fault (SSF) approach. To be certain that all sorts of faults and their effects can be detected, these should include transition, path delay, hold time, slack-based, static bridging, dynamic bridging, cell-aware, and IDDQ models. The transition from functional simulation to fault simulation must be seamless to eliminate spurious mismatches.
It must be possible to insert the test logic structures into the chip design with minimal manual effort. This includes LBIST, MBIST, ECC, processor interfaces, and debug via a test access port (TAP). Since on-chip memory is limited, the structures must also support comprehensive at-speed testing of external DRAM and high-speed memory interfaces. Many of these functions can be provided by proven IP libraries and by design for test (DFT) tools that insert the desired structures automatically as part of the design process.
Meeting all the requirements mentioned so far requires a broad solution, and fortunately there is one available. The Synopsys TestMAX test automation family is the heart of the solution. In concert with Synopsys VC Functional Safety Manager, it provides all the testability analysis required by ISO 26262. It performs DFT to insert the test structures, runs automated test pattern generation (ATPG), and converts the patterns into formats needed for the manufacturing floor. Synopsys Z01X is responsible for injecting faults and grading the effectiveness of the tests.
The solution’s LBIST capabilities support a diverse range of applications, including:
The solution comes with ready-to-use scripts for test planning, generation, insertion, and verification. SMS Silicon Browser supports post-silicon bring-up, debug, diagnostics, and characterization. Finally, Synopsys SMS IP is a comprehensive, integrated test, repair, and diagnostics solution supporting both embedded and off-chip memory. It goes beyond test and diagnosis to actually repair memories with that capability.
Chips for automotive applications have a high bar for reliability and functional safety, placing high demands on testing them both in manufacturing and in the field. Synopsys TestMAX is a proven solution certified to satisfy ISO 26262 up to ASIL D (“safety critical”). It supports operation at the RTL stage to enable early validation of DFT and safety mechanisms. In-field testing and safety are key parts of support for silicon lifecycle management (SLM). There is no better way to develop automotive chips with minimal manual effort, minimal schedule impact, and minimal PPA impact while meeting all the requirements of the market.
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