The Design Automation Conference Turns 60! What’s Hot? What’s Next?

This coming week from July 9^th to July 13^th, experts from all over the world will descend on the Moscone Center in San Francisco to discuss aspects of what we call “Electronic Design Automation” (EDA) and typically associate with hardware development. There will be many celebratory elements this year, given the milestone of 60 years. Industry luminary Alberto Sangiovanni Vincentelli will give one of the keynotes called “Corsi e Ricorsi: Here We Go Again.” Some presentations will likely worry about staffing – Joe Sawicki‘s talk is titled “Systems 2030 – What’s Needed to Succeed in the Next Decade of Design without Resorting to Human Cloning,” only to be followed later in the week by a glimmer of hope for the future of EDA with a talk by the youngest presenter, ever, at DAC. Ham Radio Operator (KJ7NLL) Zeke Wheeler will use his summer break at school to talk about his efforts to speak to space with self-built equipment in his talk “DIY Orbital Tracking System for Space Communication: A Project to Contact the International Space Station.”

DAC’s 60th anniversary highlights.

What happened to system design and system on chip (SoC) integration?

For me, this will be the 25^th DAC that I am attending. During my first DAC in 1998, Gary Smith had just coined the term “Electronic System Level” (ESL), and High-Level Synthesis was the year’s hot topic. The industry has made great strides since then, albeit not always in the predicted direction. High-level synthesis has “simply” become the front end for digital implementation flows. It has never grown up to synthesize many whole chips, but it is these days critical to block development, porting between semiconductor technologies, and Engineering Change Order (ECO) management.

Another topic – the increased criticality of hardware/software co-design and the complexity of chip integration – was on the horizon back then already and will be a key theme at this year’s DAC, too, um, still. Modern System-on-Chip (SoC) devices involve hundreds of functional intellectual property (IP) blocks, including externally acquired and internally developed ones. These blocks require careful integration to ensure the SoC operates effectively. And the trend towards chipset-based design – probably the hottest topic this DAC – only amplifies this trend as design teams consider integration across chip boundaries.

SoC integration involves managing extensive metadata that describes each IP and has been mostly a manual process in the past, leading to data alignment challenges and a lack of a single source of truth. Manual approaches often resulted in missed deadlines and failed revenue targets. The “Virtual Socket Interface Alliance” was a hot topic in 1998. Since then, a solution came with IP-XACT, a metadata format developed to manage and integrate SoC IPs. While IP-XACT specifies metadata representation, design teams need the appropriate tools and environment to utilize it fully. Companies that had to automate complex, error-prone tasks, ensure repeatability, and streamline the IP integration process have often created proprietary infrastructures that can become complex and difficult to maintain, especially for startups.

Arteris will show at this DAC its SoC integration offerings allowing design teams to build their automation infrastructure and facilitate SoC integration based on a single source of truth. They can seamlessly integrate IPs regardless of their IP-XACT model status, ensuring their semantic and syntactic correctness. The Magillem toolset helps users create the design hierarchy for integrating all IPs. It’s about connecting different IPs and configuring and instantiating each IP, creating interfaces, and building each IP into the design hierarchy. The Magillem toolset adapts to the underlying interconnect fabrics used by the SoC designers – like FlexNoC and Ncore – and provides ways to rearrange the design hierarchy easily. This capability assists design teams in upgrading individual IPs and organizing their physical layout and can be fully automated and used in a continuous integration pipeline.

Hardware/software co-design is a critical part of SoC integration and plays a role here too. Magillem Registers translates the specification of registers into executable design code by automatically importing the register descriptions from different sources and formats into IP-XACT. It automatically checks the accuracy of the information – like overlaps, configurability, reserved empty spaces, and more – and enables close collaboration between hardware, software, and tech doc teams through a single source of truth methodology for consistently generated data. Applying this process results in better quality design and increased productivity.

An example of a design flow with a single source of truth. (Source: Arteris)

The IP Engineering Track at DAC

For my 25^th DAC, I was invited as a member of the Executive Committee to chair the IP portion of the Engineering Track. Like the DAC research track overall, the Engineering track saw a significant increase in submissions for its 60^th birthday. With the help of my extraordinary Technical Program Committee (TPC) Himanshu Sanghavi, Navid Farazmand, Vidyasagar Ganesan, Randy Fish, and Shankar Hemmady, led by Henning Spruth as TPC chair, we came up with a program I am very proud of.

For this year’s IP Engineering Track, we selected 24 presentations in four sessions:

• Advanced Front-End Verification for Leading-Edge IP
• Advanced Verification for Leading-Edge IP – Memories, FPUs, and Security
• Leading Edge Implementation for IP
• Groundbreaking Results for Leading Edge IP

A technical introduction to UCIe aligned with chiplets as one of the hottest topics at DAC, a panel on RISC-V, and a discussion on security in the world of IP round up the IP Engineering Track:

• Everything You Should Know about UCie
• Delivering on RISC V’s Promise to Give Designers Freedom to Innovate – What’s Needed?
• Securing IP in the Cloud

What’s next

We live in genuinely unique times for semiconductor design. Artificial intelligence and machine learning (AI/ML) for EDA development and EDA development to enable AI/ML semiconductor components seem to create a circular loop that only gets faster.

Traditional printed circuit board (PCB) design and semiconductor development move closer to each other as PCBs get smaller and become chiplet-based designs while in parallel, SoCs meet the reticle cost/yield limits and disaggregate, you guessed it, into chiplet-based designs, too.

Beyond the classic EDA topics, we have application-specific designs for automotive, enterprise computing, data center, industrial, and consumer applications, horizontal solutions for security, safety, and hardware/software, and of course, the move toward system design, including mechanical, EM and many more aspects to consider. And then, there are the impacts of generative AI, workforce development, and many other items to discuss.

DAC is the place to be next week. I look forward to celebrating DAC’s 60^th birthday with you and discussing how EDA will shape the next decade.