The Growing Importance Of Subsystems

Complexity and time-to-market demands are driving the IP market toward much greater up-front integration.


By Ed Sperling
A growing reliance on third-party IP is beginning to expand well beyond just IP blocks and into full subsystems, opening significant growth opportunities for companies competing in this market as well as enormous business and technical challenges.

The IP market is ripe for this kind of convergence. Complexity at advanced process nodes coupled with time-to-market demands has elevated third-party IP from an emergency fix inside most designs to a necessity. By some reports IP now accounts for up to 90% of an SoC design. What’s changing is that IP increasingly is being integrated with other IP, software and even hard IP, so it can be plugged into an SoC with far fewer integration problems associated with single IP blocks.

“What’s driving this are the tablet and smart phone markets,” said Prasad Subramaniam, vice president of design technology at eSilicon. “Those are the highest growth markets, and companies like ARM and MIPS are creating blocks around their cores to harden and pre-verify. We’re even seeing this happening with entire reference designs, which include those subsystems. In the past this was just a reference design. But there are a lot of OEMs—especially Asian companies—that don’t have the resources to do these designs from scratch, so they’re picking up the design and fixing whatever is necessary to get to market quickly.”

James Mac Hale, vice president of Asia operations at Sonics, had a similar view: “We’ve seen SoCs move from integrating cores to subsystems. The number of cores is going up, and so is the complexity and desire for re-use. The challenge is that once you combine all these subsystems, how do you design the overall system behavior. Each reacts differently on its own.”

Getting a handle on the changes in this market is no simple task, in part because this trend is just beginning to take shape and in part because of the breadth of what’s happening. Even defining IP can lead to arguments about what is and is not considered commercial intellectual property. Adding more pieces into the mix only confuses the definition.

Synopsys, for one, defines IP subsystems based upon function. That definition includes the integration of one or more pieces of IP with the software stack running on top of it, all of which is configured for a specific application. That could be an audio-based subsystem with an ARC processor, the necessary codecs, interconnects for such things as a headset or speakers, or it could be a USB subsystem with the controller, PHY, a software stack on the USB, integration services and verification IP, according to John Koeter, vice president of marketing for IP and systems at Synopsys.

“The majority of IP is still going through traditional sales channels,” said Koeter. By our best estimates, about 5% of the IP market today is made up of IP subsystems. Over the next three years we expect that to double or triple.”

Exactly what those subsystems evolve into, however, is anyone’s guess. “One way to look at this is that right now you have semiconductor IP like USBs or memory, and at the other end you have platform-based deisgn, which is architectural re-use but not IP,” said Mike Gianfagna, vice president of marketing at Atrenta. “The subsystem is what’s in between. What’s interesting about all of this is that a few years ago what we now consider a subsystem was a full chip.”

Business challenges and changes
As the market for subsystems grows it also will create significant fallout across the industry, which is why chipmakers, IP developers and tools companies all are scrambling to position themselves for this shift. Rather than just another form of outsourcing of pre-developed IP, the convergence of multiple IP blocks, development tools, software and even services threatens to shake up the power structure in this segment of the industry.

It’s not certain at this point who will lead the subsystems effort, and whether the leaders will emerge from existing IP vendors, software developers, tools companies, or some combination of all three that has yet to come together.

Neil Hand, group director for marketing inside of Cadence’s SoC realization group, believes that while foundries are well equipped to deliver IP the EDA companies are better equipped to deliver a subsystem. “This is the functional space, which is where EDA companies live,” Hand said. “They can combine IP with high-level synthesis and high-level modeling. It’s a natural direction for EDA companies to be working with IP.”

eSilicon’s Subramaniam believes it also could be the chip companies that ultimately sell the combined subsystems. “I see the chip companies becoming more like IP companies, particularly as 3D stacking evolves,” he said. “You might see memory companies initially, but it also could be analog companies or an RF company selling the subsystems.”

At least part of what will drive these changes is the push toward Wide I/O and the recognition that multicore and many-core strategies need to be re-evaluated. The initial idea behind multicore was that either software would be written in parallel or that virtualization would work when parallelization wasn’t possible. Despite the devotion of enormous resources to parallelization of software, the best that companies have been muster for many applications is to thread certain functions onto two or four cores. In a 16-core processor, that still leaves 12 cores idle.

Virtualization hasn’t worked out as planned, either, despite its success in the server world. The solution in enterprise IT departments has been to virtualize servers to improve utilization of the servers, which typically had been running at 5% to 15% of capacity, by most industry estimates. While that improved efficiency in large server farms with thousands of server racks, because it reduced cooling costs and the cost of powering the servers, the strategy is actually inefficient at the processor level because all the cores must be homogeneous and too many need to be in the “on” state to take advantage of this approach. Moreover, one of the limitations of multicore and many-core systems is the shared memory.

With wide I/O, more dedicated memory and heterogeneous cores sized for specific applications, performance can be ratcheted up significantly while simultaneously reducing power. That basically turns a core into a subsystem, and one that may or may not be independently designed by a third party and tweaked slightly for re-use.

“The tricky part is what happens near the interface,” Gianfagna said. “Timing, power and the performance of a subsystem, or even a block, are now affected by its neighbors. That means you have to re-check it in the context of full chip integration. We will need tools at the subsystem and the system level to do that. In my opinion, that’s a huge opportunity for EDA. It’s also a modeling and methodology challenge.”

Signal traffic also is affected. Sonics’ Mac Hale said connectivity is one of the top issues that needs to be addressed as IP is combined into subsystems. “We need much more flexible interfaces to deal with this,” he said. “System-level IP is becoming much more important these days, and that includes subsystems. We need to understand how different subsystems interact.”

Impact of 3D stacking
3D stacking and Wide I/O are expected to bolster sales of pre-integrated IP even more. While solving the issue of traffic bottlenecks, they also significantly raise the complexity of the interactions.

“It’s not really off-the-shelf subsystems,” said Cadence’s Hand. “They have to be tweaked by traffic patterns. Long-term there may be a whole memory subsystem, but right now it’s getting together pieces that work. That could include a Qualcomm baseband subsystem, which is incredibly complex. It also could be a compute subsystem that includes a processor and graphics chip. But while there is a demand for off-the-shelf IP that works together, customers are still wary
of taking everything off the shelf.”

In one respect this is a significant market shift. From an EDA tools perspective, however, it amounts to a tweak—at least for the moment.

Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics, said that whether it’s blocks or subsystems or even moving devices onto printed circuit boards, the basic idea hasn’t changed. As a result he believes many of tools at the back end of the design should work fine—at least until stacking of chips begins over the next couple years.

“At that point you’re going to be doing the kind of make vs. buy decisions that you’re doing now with third-party IP, but it could be a proven die instead of IP,” Buehler-Garcia said. “From an EDA perspective, until you are doing tradeoff analysis and tuning with the TSV (through-silicon via), the tools we have now will work with extra scripts.”

The push toward subsystems will continue unfolding over the next few years, driven by ever-increasingly complexity and an understanding of where companies truly add value and where they’re adding a function that is required by a particular market segment. That makes subsystems a design shortcut, and one that is particularly useful when the marketing department adds another requirement late in the design cycle.

“An IP subsystem becomes the bridge between the system-level design and the implementation,” said Synopsys’ Koeter. “You get a virtualized model of the IP subsystem, accelerated chip-level verification and you start seeing software integration of the stack.

It also becomes a business opportunity in its own right for companies that can build these flexible subsystems, and for those that can sell them in a coherent way.

“The market opportunity is for a catalog of proven silicon so you pick out what you want,” said Mentor’s Buehler-Garcia. “That is a quick way to get to market.”

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