The Impact Of 5G On Silicon Design

Bandwidth, latency, and power consumption are the primary challenges for upcoming 5G designs.


5G, the next-generation of mobile broadband, is driving tremendous increases in data throughput for mobile applications by introducing carrier aggregation, massive MIMO, advanced modulation, and high bandwidth channels in the mmWave spectrum. However, 5G and its governing body, 3GPP, has very high expectations to expand its capabilities well beyond the mobile market, and move into many new areas, including low-power Internet of Things (IoT) applications such as asset tracking, autonomous vehicle connectivity like vehicle to infrastructure, broadband internet services, cable television services, and much more.

China Mobile, China Telecom, and China Unicom launched 5G services in November 2019 with more than 9 million subscribers. Ericsson believes that over 2.6 billion subscriptions will be based on 5G in the next six years. In order to provide these subscriptions, hardware is already aggressively being developed for 5G applications and the infrastructure that 5G requires. There are already 5G-capable baseband solutions being deployed in today’s phones. These baseband solutions provide the technological upgrades that drives 5G adoption and are essential for high bandwidth, feature-rich wireless communications.

However, 5G impacts silicon designs well beyond baseband processors. With such wide-ranging applications to serve and ambitions to increase throughput significantly there is a total system impact that is modifying the designs of countless SoCs. These SoCs include the applications processors that must accommodate higher bandwidths and complex aggregation of communications. These applications processors are found in mobile phones, AR/VR headsets, drones, cameras, tablets, 2 in 1s, and many other consumer devices.

Beyond consumer devices there is an infrastructure that must accommodate a high density of these consumer devices and route the incoming data to the appropriate destinations. These destinations could be another network, a local device, a cloud data center, or a local data center where edge computing is a fundamental trend to support the future of distributed computing. All of these destinations are upgrading their SoCs to accommodate 5G well beyond just the baseband processor.

5G semiconductor segmentation

There are three pillars that have commonly been referred to with 5G development: Enhanced Mobile Broadband (EMBB), IoT, & Machine to Machine Communications (MMTC), and Automotive & Ultra Reliable Low Latency Communications (URLLC). Growth in these pillars will occur in waves, with EMBB applications leading the way (figure 1).

Fig. 1: IoT growth will occur in waves. Source: McKinsey

Mobile broadband is driving new application and baseband processors in the mobile phone today, with the most interesting growth in this area being the infrastructure to support it. For years we’ve been hearing about microcells (outdoor), picocells (indoor/outdoor), and femtocells (indoors). With 5G and mmWave technologies the indoor cells and small cell growth is becoming a major focus for semiconductors. This isn’t just new baseband processors. It’s the growth and idea of edge computing that will accompany all the networking capabilities in the infrastructure with the addition of servers that will manage and analyze the data locally. 5G providers have big plans to accommodate this and there have already been some server SoCs introduced that support lower power and lower latency.

In addition to the server SoCs located within the 5G infrastructure, we see the need for specialized AI accelerators to analyze the massive amount of data and provide much more valuable services in managing that data.

Beyond the high-bandwidth video applications, 5G incorporates low-power technologies such as LTE-M and NB-IoT to enable applications within the 5G infrastructure such as asset tracking, push to talk voice capabilities and location services. These low-power, minimal data nodes number in the billions and increase the traffic and capabilities of networks tremendously. SoC designs are having to accommodate the new nodes adding LTE-M and NB-IoT as well as the traffic they create within the infrastructure. In addition to the high-bandwidth and low-power IoT applications, 5G has incorporated low-latency, ultra-reliable communications for mission-critical and autonomous driving functions. These are pushing the limits of technologies and systems throughout the design world.

Three primary challenges for 5G

Bandwidth continues to dominate the conversation about 5G improvements, however latency and power consumption are two additional challenges that are required to implement 5G’s ambitious goals.

Because this is a system challenge, and not just a wireless challenge, SoC design bandwidth throughout the device is important. High bandwidth standards-based IP availability is a critical piece of the 5G SoC system design. This starts with LPDDR introductions of LPDDR4/4x and now LPDDR5 in mobile phones. DDR5 is now being adopted heavily for infrastructure 5G networking and server SoCs. MIPI has introduced higher bandwidth capabilities with CSI-2 v3, I3C and UFS 3.0 for connectivity to mobile sensors and memories. PCIe is aggressively moving to increasing bandwidths from PCIe 3 to PCIe 4 and 5. Ethernet continues to expand bandwidth and infrastructure SoCs are seeing quick migration to 400G and 800G that requires the latest high speed SerDes PHYs including 56G and 112G. Bluetooth has upgraded Bluetooth Low Energy making Bluetooth Classic obsolete as it now supports audio capabilities. USB, the fundamental connectivity in consumer devices has migrated from 3.0 to 3.1 to 3.2 and now is introducing USB 4. Beyond standards-based IP, the introduction of AI processors to handle self-organizing networks, and highly parallel vector DSP processors for the ever-increasing complexity found in baseband processing is seeing adoption in SoCs to address 5G carrier aggregation and massive MIMO processing and bandwidth needs.

As an example of lowering latencies, the current 5G spec expects round trip latencies of less than 1ms. Future 6G initiatives introduced in the fall of 2019 expect round trip latencies in the 10s of microseconds. This may be orders of magnitude more than some memory accesses within an SoC but with such low latencies every clock cycle within SoC designs is much more important. To improve latencies within SoCs there is a strong trend to use expert services to build highly integrated and optimized subsystems to lower latencies. In addition, new standards-based protocols are being adopted specifically to improve latency such as CXL. Synopsys is a leader in providing optimized systems to reduce latency including industry leading low latency DDR controllers, newly adopted CXL controllers that perform well below the minimum specification, and processing and interface subsystems that remove bus fabrics and map registers directly into the processor in addition to tightly coupling memories.

Power consumption
To expand mobile providers ability to service the Internet of Things, low power protocols such as LTE-M and NB-IoT have been introduced. These protocols require new processing solutions, new radio solutions and low-power system design methodologies and IP capabilities including operation at near-threshold voltages, voltage and frequency scaling, and intelligent clock gating.

5G SoC impact summary

5G is introducing a wide array of challenges in next-generation SoCs that go well beyond high bandwidth wireless. These include increasing system bandwidth, lowering SoC latency, and reducing power significantly for the connected internet of things. Using trusted standards-based IP and proven processing and analog IP at the most aggressive process technology nodes is needed to bring 5G to market. Synopsys provides the most comprehensive IP portfolio for 5G implementations and can be found most of the implementations globally. To learn more, read the white paper “How 5G is Influencing Silicon Design.”

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