The Implementation of Embedded PVT Monitoring Subsystems In Today’s Cutting Edge Technologies

How to improve performance and reliability of SoC designs.


This new whitepaper from Moortec takes a comprehensive look at the Implementation of Embedded PVT Monitoring Subsystems in Today’s Cutting Edge Technologies and how this can benefit today’s advanced node semiconductor design engineers by improving the performance and reliability of SoC designs. With advances in CMOS technology, and the scaling of transistor channel lengths to nanometer (nm) dimensions, the density of digital circuits per unit area of silicon has increased as has the process variability of devices manufactured.

The increase in digital logic (or gate) density, which equates to an increase in power density, is a major contributor to the heating of semiconductor devices manufactured on advanced node CMOS technologies. In-chip temperature monitoring is used for performance optimisation, an example being Dynamic Voltage and Frequency Scaling (DVFS) where, depending on the thermal conditions, system clocks and voltage supplies can be varied to optimise either the speed of logical operations or power consumed by the device.

Process induced variations in circuit delays have begun to significantly adversely affect chip performance and power consumption. A statistical analysis of each device would show a process variability, or spread, that when compared to historical CMOS technologies is wider (worse) for advanced technology nodes. To address this, manufacturers have to design their Systems-on-Chip (SoC) to over-compensate for unwanted variability arising from manufacturing processes. Increased logic gate density, increased track and via impedances and process variability has led to significant voltage (IR) drops across advanced node devices. Together with an increasingly noisy environment, the need to monitor core supplies in-chip has become desirable to ensure that operating conditions are acceptable to the complex systems in today’s devices.

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