The Importance Of Metal Stack Compatibility For Semi IP

Reducing the number of metal layers used by eFPGA.


Every foundry and every node is different, but for every foundry/node there are multiple supported metal stacks.

Some chips use a lot more metal layers than others. A common rule of thumb is each metal layer increases wafer cost 10%. So, a chip with 5 more metal layers than another will cost 50%+ more.

The most complex, high performance chips, including performance FPGAs, typically use ALL of the metal layers available in a process node for maximum routability.

More cost sensitive chips set out to use as few layers as possible to keep costs low.

Short distance routes prefer one type of metallization; long distance routes another type. Power/Ground layers are thick metal.

But it’s not just cost and digital routing: Analog chips need certain types of metal to construct their circuits.

So, an advanced finFET node process may have several dozen available metal stacks to choose from.

Semi IP metal stack compatibility

When our customers first meet us, they typically have selected a foundry/node/metal stack or a small number of options and we must be compatible with their needs.

An eFPGA IP from an FPGA manufacturer will typically use all of the metal layers in a finFET node because they are giving you a “slice” of their own FPGA. This means you must a) use the maximum number of metal layers, perhaps increasing your metal stack 3-5 layers more than you need and b) adopt all of their metal layers, which can be a show stopper if you are doing analog, etc.

EFLX eFPGA uses many fewer metal layers and is typically compatible with a majority of the available metal stacks. This is because of our patented XFLX interconnect, which uses half the metal layers and half the transistors of the traditional FPGA interconnect.

We build EFLX eFPGA using foundry standard cells then add a few layers of routing: in 40nm we take up 6 layers of metal, in 7nm we take up 9 layers of metal. So, we can be compatible even with low cost SoCs.

Even with this big advantage, we still achieve logic density and performance the same as high performance FPGAs, so you lose nothing but can build with the metal layers you prefer and with fewer metal layers for lower cost.

See our website for the exact metal stack for EFLX eFPGA on multiple foundries and nodes:

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