The Power Treadmill

By Frank Ferro
The recent purchase of an LTE smart phone has me back on my power management soapbox. I upgraded my phone about a month ago to the newest version (staying with the same manufacturer as my previous device) and to my dismay, although it wasn’t completely unexpected, the battery life was actually shorter. I did not do a ‘scientific’ comparison, but following the same daily use pattern I noticed the battery life percentage indicator was much lower at the end of the day when compared to my two-year-old 3G model.

The reason I say this was not completely unexpected is because in my February 2013 SLD blog (Power Management: Throwing Down the Gauntlet) I sighted a recent survey showing that users of 4G phones were less satisfied with the battery life than were users of 3G phones. This was due to the fact that the radio needed to wake-up more often to look for a 4G base station. I also suspect that the larger screen is another key contributor.

Instead of speculating (and complaining) about battery life, let’s take a look at the power profile of a smart phone to determine where we can get the most ‘bang for the buck’ when looking for places to save power. The table below is from an article in the November 2012 Microwave Journal showing the power profile of major components in a smart phone. As the table shows, the overall power consumption over the last few years has nearly doubled. According to the same article, battery capacity has been increasing by about 10% per year for the last few years, so the battery technology has not been able to keep pace with the smart phone power requirements.

Note that battery life is a function of phone use cases scenarios, with such activities as voice calls, video calls (e.g. Skype or FaceTime), using the Bluetooth headset, Wi-Fi, watching videos, listening to audio, etc. Each of these use cases puts different loads on the CPU, GPU, display and the various radios, so the table provides a general idea of the overall power profile for a given use case.

As suspected, the radio takes a reasonably large percentage of the power (23%), but the rate that RF power has been increasing with each new technology node is relatively low at 11%. The largest rate increase has been in the display at 300%, which should not surprise anyone given the size and the resolution of the smart phone displays. And consider that the data in this chart does not take into account some of the most recent smartphone models having even larger displays with better resolution.

Looking next at the processor and peripherals we see that together they account for more than half of the power consumption, so clearly targeting these components for better power management will have a significant benefit to the overall battery life. The problem, however, is that new smartphone processors keep increasing in speed and adding more processor cores and GPUs, so the power treadmill is not slowing down.

Is help on the way?
One obvious solution is better battery technology. Recent research claims that lithium-ion micro-batteries will provide a 10x power improvement or be 10 times smaller than today’s batteries—take your pick. Given that these batteries are still in the research stage, don’t expect to see commercial products anytime soon. Consequently, we need to look at the silicon for some immediate relief.

Silicon providers traditionally have relied on process technology progression to reduce power (usually with lower operating voltage), but at 40nm process nodes and smaller there is limited help because leakage power has become difficult to control. If not properly managed, leakage power can exceed dynamic power. New process techniques such as silicon on insulator (SOI) have helped, and the new FinFET technology offers improved leakage, but we have to wait a bit longer for full production of FinFETs.

So where can we expect to get the most immediate and largest improvements in silicon power consumption? Looking at the above graph, the highest power consumption gains can be achieved with architectures that comprehend power management (left side of the graph). SoC designers must incorporate power management techniques early in the design phase as a fundamental part of the architecture, and not look for power optimization later during the silicon implementation phase (right side of graph). Techniques such as power shutoff, adaptive voltage scaling (AVS), dynamic voltage and frequency scaling (DVFS) and clock gating are in fact being used in various combinations in the latest smartphone SoCs. These techniques are good, but are they enough to keep up with the treadmill?

Other than CPF and UPF, which only specify power intent, there is not a standard methodology for implementing a power management architecture. For example, AVS and DVFS lower power consumption, but at the cost of increased system complexity. Therefore, without a standard methodology AVS and DVFS are used sparingly in the system to trade off design complexity with power savings. In addition to the hardware, software complexity also increases as more aggressive power management is applied to the system. To take full advantage these and other power saving techniques, design tools and IP are needed to allow SoC designers to deploy better power management without the design risk. Applying a standard methodology will simplify development, especially for design teams that are not familiar with power management, and increase thier ability to verify functionality and performance of the power management network.

So maybe (just maybe), two years from now when my phone contract expires, I will be able to purchase a smart phone that actually will have longer battery life. This only will be possible, however, with a combination of improved battery technology, process technology and better SoC power architectures. Given the SoC design cycle time, better SoC power architecture work needs to start right now in order for these SoCs to be in smart phones by March 2015— my current phone contract expiration date—or I will have to wait another two years…

—Frank Ferro is director of product marketing at Sonics.