The Roadmap To 5nm

By Debra Vogler
Among the challenges the semiconductor industry will be facing as it moves down the path to node 5 are resistance-capacitance (RC) management and integration. SEMI is pleased to announce a SEMICON West 2015 STS technical program exploring these and other high-volume manufacturing challenges.

According to An Steegen, SVP of Process Technology at imec, the list of RC management challenges includes, but is not limited to: 1) Low-k spacers and wraparound contacts; 2) Improved metallization for the back end; 3) Air gaps to improve the capacitance; and 4) Self-aligned contact and vias as a way to further scale. “Integration ‘tricks’ will also be needed to improve selectivity between different kinds of materials. The more you get into 3D types of device architectures, the more you need to manage the RC, and that starts in the front end with how to manage the capacitance,” said Steegan. See Figure 1.

Figure 1: Imec logic device roadmap; device technology features. SOURCE: Imec/ITF Korea 2015.

Steegen, who will be presenting at SEMICON West 2015, also noted that other process parameters to improve the power performance of the transistor are novel device architecture such as nanowires, and high-mobility materials such as Ge and III-Vs. The move from a FinFET to lateral nano-wires will be gradual, she said, and the trend in channel materials will see epitaxially-grown materials to improve strain, i.e., Ge, SiGe, and III-Vs. “If you mix all of that together, you get a pretty clear view in going from 10nm to 5nm.”

Cost-Effective Patterning
Steegen also told SEMI that the 10nm node is the ideal node to introduce EUVL (Figure 2). “When you introduce EUV at 10nm, you can go to a single exposure for almost every critical level,” said Steegen. “The question for the industry is that by the time that 10nm gets to HVM, can insertion of EUV still be a cost reduction driver?” Putting the status of EUVL into perspective, she noted that recent news releases regarding 16nm (for foundries) and 14nm (for IDMs) place these nodes in early production. So at 10nm, she expects early production to be in the 2017-2018 timeframe, and HVM to be in the 2020 timeframe. “There is still some time to get EUVL to HVM.”

Figure 2: Imec logic lithography roadmap. SOURCE: imec/ITF Korea 2015.

Imec has done a full N10 immersion multi-patterning vs. EUV assessment to investigate the trade-offs between both patterning techniques. “It is feasible to insert EUVL at the most critical levels later on in the N10 production cycle,” noted Steegen. “If a 0.7x liner is implemented at 7nm, EUV will be needed even more to avoid an ever greater complex multi-patterning integration and cost increase.” Imec is in the process of full EUV assessment for insertion into fully-scaled N7 and N5 technology nodes she told SEMI. “We believe there is still time for the industry to continue with the progress it’s been making on EUVL, especially with respect to throughput.”

As for that fast-moving patterning technology – DSA (Directed Self Assembly) – Steegen noted that while great progress has been made, a number of investigations need to proceed, most notably, defectivity and alignment accuracy, as well as design rules and integration. She expects that feasibility checkpoints for DSA at node 7 will be completed by imec later this year. “We should be able to prove these checkpoints for DSA at certain levels this year, but, it’s for the industry to determine how soon it will pick it up for its different process flows,” said Steegen.

The Path to 5nm: Innovation at Many Steps
Steegen told SEMI that the roadmap [to 5nm] is impossible to summarize in a one-liner. “Imec is enabling the roadmap to 5nm via a multitude of process features in close co-optimization with the design to drive down to the required power performance and cost tradeoffs,” Steegen noted. “We are convinced that we have identified building blocks to enable the roadmap from 10 to beyond 5nm. But it’s not a one-solution thing – it’s many things that need to come together.”

SEMICON West 2015 will feature An Steegen – plus Juan Rey, sr. director, Calibre Engineering and Mentor Graphics and Harmeet Singh, corporate VP at Lam Research – in the “Scaling Transistors: HVM Solutions below 14nm; Getting to 5nm” session on Wednesday, July 15. Learn more at www.semiconwest.org.