The Shortest Path Deception

When manufacturing, assembling, and using integrated circuit (IC) chips, the electrostatic discharge (ESD) caused by accumulated static can damage the IC circuitry if the circuit is not properly protected [1]. To prevent such damage, ESD protection devices are designed into the circuitry such that they will create a low impedance path that limits the peak voltage and current by diverting excess electric current away from the protected circuitry during an ESD event. Creation of the low-impedance path is done using multiple parallel routes to create an effective and efficient ESD discharge path. For ESD protection to work effectively, the resistance of an ESD discharge path must be below a certain threshold, as specified in the design rules.

Multi-path resistance structures

The point-to-point (P2P) flow of this discharge path is one of the design verification flows that can be used to check the resistances of these multi-path structures at the intellectual property (IP), block, and full-chip levels of IC designs. The P2P flow simulates the effective resistance between two electrical terminals, such as an ESD source (e.g., a physical pad) and its ESD protection device, and flags a violation if the resistance value exceeds the defined design limit [2].

Figure 1 illustrates some typical ESD protection schemes and common ESD discharge paths [3-4]. In figure 1a-d, the I/O pad is protected by pull-up and pull-down diodes, an ESD resistor, and secondary ESD diodes, and a power clamp is connected between the power bus VDD and ground bus VSS. In figure 1e, a pair of back-to-back (B2B) connected diodes are used to connect the ground busses VSS_A and VSS_B from two power domains.

Fig. 1: Typical ESD protection schemes.

When P2P resistance violations are found, designers must modify the layout design to lower the resistances on the violating ESD path. However, before designers can fix a layout, they need information that can help them find the resistance bottlenecks in the ESD paths. This is where designers can be misled by information that appears to be useful but is actually not relevant to accurately fixing resistances on these multi-path ESD structures. Such information typically includes:

• a highlight of the shortest path between an ESD source and its ESD protection device
• a breakdown of the sums of resistances by metal and via layers, etc.

Let’s take a look at why this data is not only unhelpful but may actually impede accurate multi-path debugging and fixes. Then we’ll talk about solutions, including an automated checking and debugging solution based on the Calibre PERC reliability platform from Siemens EDA.

Is the shortest path data useful?

Shortest path
Does knowing the shortest path help in debugging a resistance violation, particularly when it comprises multiple paths? (Hint: the answer is no). Figures 2 and 3 explain why. Figure 2 shows a multi-path resistance check between two electrical terminals A (source) and B (sink). The route between A and B consists of metal1, via1, and metal2 layers.

Fig. 2: Multi-path resistance check between two electrical terminals A (source) and B (sink).

In our example, each of the ten metal1 segments (which are electrically shorted at B) has a resistance of 10 ohms, each of the 100 via1s have a resistance of 80 ohms, and the metal2 segment has a resistance of 5 ohms. The ESD design rule of our hypothetical case says that the resistance between A and B must not exceed 2.5 ohms.

Taking into consideration all resistances in parallel and in series, the total effective resistance (R_AB) is calculated as follows:

• ten metal1 segments in parallel add 10 ohms/10 = 1 ohm
• 100 via1s in parallel add 80 ohms/100 = 0.8 ohms
• the metal2 segment adds 5 ohms
• total effective resistance R_AB = 1 + 0.8 + 5 = 8 ohms.

We can quickly see that the majority of R_AB comes from the metal2 segment, which adds 5 ohms to this simple multi-path structure.

The shortest path between A and B includes one metal1 segment (10 ohms), one via1 (80 ohms), and the metal2 segment (5 ohms), as shown in figure 3.

Fig. 3: Shortest path.

If designers make the mistake of only looking at the resistances of the segments on the shortest path, they might conclude that to fix the resistance violation between A and B, they should reduce the resistances from the via1 and/or metal1 segment, since these two segments have the highest resistances. However, no matter how much you reduce the resistances of metal1 and/or via1 layers, either by reducing the lengths of metal1 segments or adding parallel routes to metal1 segments and/or via1’s, the total effective resistance R_AB will remain at >5 ohms, due to the resistance from the metal2 segment alone. The shortest path approach is a dead-end road.

Sum of resistance by layer
If the shortest path isn’t useful, what about using the sum of resistance by layer? Turns out, that’s not helpful either. The route between A and B consists of metal1, via1, and metal2 layers. The sum of resistances by metal1, via1, and metal2 layers, respectively, is approximately:

• 100 ohms (10 ohms x 10 = 100 ohms)
• 8000 ohms (80 ohms x 100 = 8000 ohms)
• 5 ohms

Based on the sum of resistance by layer, designers might try to fix the resistance violation between A and B by reducing the resistances on via1 and/or metal1 layers, as these two layers have the highest sums of resistance. However, as we pointed out, no matter how much you reduce the resistances from metal1 and/or via1 layers, the total effective resistance R_AB is always going to be > 5 ohms, due to the resistance of the metal2 segment. Once again, designers have been led down a false path.

To correctly fix the resistance violation between A and B, designers should add parallel metal2 segments. If they add nine metal2 segments for a total of ten metal2 segments in parallel (which are all electrically shorted at A), then these ten metal2 segments now have a total resistance of 5 ohms/10 = 0.5 ohms, down 4.5 ohms from the previous 5 ohms. With this fix, R_AB is reduced to approximately 2.3 ohms (R_AB = 1 + 0.8 + 0.5 = 2.3 ohms), which falls below the design rule constraint of 2.5 ohms, fixing the violation.

Automated resistance checking and debug

As we’ve shown, finding the correct solution to resistance violations can be tricky. Automated electronic design automation (EDA) solutions are available that can help designers avoid these deceptive data traps and find the correct solutions quickly and easily. We’ll look at one solution from Siemens EDA that provides visual debug guidance to help direct designers to the best fix in less time.

P2P resistance debug flow
The Calibre PERC reliability platform provides a P2P automated debug flow with visual debug guidance, delivering a fast, accurate, and practical solution to debugging P2P violations in IC layout designs. Working seamlessly with the Calibre RVE results viewer and Calibre DESIGNrev layout viewer, the Calibre PERC P2P debug flow helps designers quickly locate problematic layouts and identify resistance bottlenecks that require fixing [2].

The Calibre PERC P2P debug flow automatically generates debug information that is used to highlight an entire path containing a resistance violation in the Calibre DESIGNrev layout viewer (figure 4).

Fig. 4: A complete ESD path between an I/O pad “INA” and a pull-down ESD diode that contains a resistance violation is highlighted in the Calibre DESIGNrev layout viewer.

The Calibre PERC P2P debug flow also reports information such as the percentage contribution of each metal and via polygon to the total effective resistance of a path. Using the colormap feature from the Calibre RVE results viewer, designers can highlight the metal and via polygons along the path in Calibre DESIGNrev layout viewer, using different colors based on each polygon’s percentage contribution to the total effective resistance (figure 5). The percentage range of each color can be adjusted to suit the viewer’s preferences or requirements. The polygon segments contributing the highest percentages to the total effective resistance are usually the resistance bottlenecks on the ESD path.

Fig. 5: The polygon segments of the ESD discharge path between the I/O pad “INA” and the pull-down diode are highlighted in different colors, with red indicating the highest percentage contributions, and blue the lowest percentage contributions.

This highlight capability provides a useful visual aid to layout designers when tracing a path and determining the optimal fixes, especially in a large and complex layout design such as a full chip layout database.

Summary

Checking the resistances on design-critical paths that contain multi-path structures, such as ESD discharge paths, helps ensure both the physical and performance reliability of today’s IC chip designs. When fixing these resistance violations, knowing what relevant information to look for (and what information to disregard) can significantly improve efficiency and accuracy in debugging, which in turn helps shorten tapeout schedules. Automated resistance checking and debug solutions, such as the Calibre PERC P2P debug flow, help IC chip designers quickly locate and correctly fix resistance bottlenecks, providing an accurate and dependable solution to resistance debugging, especially in large designs and full chip layouts.

References

1. D. Yan, “Ensuring Robust ESD Protection in IC Designs,” Siemens Digital Industries Software, 2017.
2. D. Yan, “Checking ESD Path Resistance in IC Designs,” Siemens Digital Industries Software, 2020.
3. EDA Tool Working Group (ESD Association), “ESD Association Technical Report,” ESD TR18.0-01-14.
4. N. Chang, Y. Liao, Y. Li, P. Johari, and A. Sarkar, “Efficient Multi-domain ESD Analysis and Verification for Large SoC Designs,” Proc. of 33rd EOS/ESD Symposium, pp. 1-7, 2011.