The Sky Isn’t Falling

While challenges abound to make true 3D ICs a reality, the industry is rallying to make it all possible.


By Ann Steffora Mutschler
3D ICs add a new dimension to design with new degrees of freedom possible, even with the added design and manufacturing complexities. Looking at the semiconductor ecosystem today and anticipating what will be needed to enable 3D ICs, it is certain that relationships will need to change. What will be required of the players and who will take responsibility for what?

Sylvan Kaiser, chief technology officer at Docea Power, observed that this new era of design will be a significant shift EDA providers because they will need to change tools to accommodate 3D designs. “Perhaps new companies within EDA will really specialize in 3D because there are new concerns, and the EDA market today probably cannot really tackle them. The system designers, chip designers, the fab, test companies, package and test companies—I’m afraid all of these have to be involved in 3D design. There will be some new need for collaboration between entities. Lots of different kinds of companies will be involved, and they have to work together.”

But what exactly is 3D? It depends on whom you ask. “There is 2.5D and more advanced 3D,” said Ahmed Jerraya, director of strategic design programs at CEA-Leti. “In 2.5D you are putting chips on an interposer. Today we are putting these on passive interposers, and in the near future I’m sure that there will be some active interposer. For this the value chain seems to be set up for the industry. But it’s not yet clear for EDA. We have several good pieces today, but it’s still not completely clear. Today you find services through companies like TSMC or through OSATs like Amkor that are able to handle this. The scheme is very similar to an advanced PCB. In fact, where you have system houses in charge of composing the overall system, they secure procurement of different chips and assembling by the packaging house, and the OSATs or TSMC are in charge of fabricating the substrate and putting the chips on the substrates. It’s very close to the process of putting a chip on a PCB.”

Steve Smith, senior director for 3D-IC strategy at Synopsys agreed. “I don’t think fundamentally the ownership rules have changed. The guy with the money is the end user of the silicon, the package and so on. In a chip manufacturing environment, maybe a fabless chip company is responsible for the entire procurement process so they might buy wafers, they might buy diced parts, and they will pick a packaging company to package that together. They have to design the package, so they are responsible for that. They are responsible for providing test vectors to test it maybe in an outsourced OSAT.”

There is another wrinkle in this for the customer. In addition to figuring out which partners to spend their money with for the manufacturing process, they now have to manage the logistics of it. “With shipping of the wafers, do they want to take the risk of shipping bare wafers that have already been thinned? Or do they make the decision based on the risk that they ship it before thinning and have the thinning done somewhere else? I don’t think these are fundamentally difficult decision. I think you can probably do that in a spreadsheet or through your personal relationships. You probably build it based on trust, of course,” he noted.

A lot of this is certainly done by contract but in reality, its trust and repeatability, Smith noted. “It’s pretty much how we’ve done business for a long, long time in EDA. Companies will buy our software but because its software, everybody knows software has special features that we sometimes call defects or missing features or enhancements and there’s an underlying philosophy in the industry that says, ‘Well, we may not have everything today but we have enough to get you started with.’”

That said, he believes there is enough of a toolkit available for 3D design today, with some examples already out there. CEA-Leti, for one, has used its engineering and manufacturing skill to build a prototype 3D IC system.

“So I don’t think the sky is falling. I think the companies that will do this, they’re about to figure it out,” Smith added.

Relationships will change
To address the new complexities, both technically and from a business standpoint, relationships between industry players will change—something that will be particularly evident with the foundries.

“One of the things that’s been very clear for the last two or three generations of semiconductor manufacturing process is that as we get down from say 40nm to 28nm and now to 20nm, the collaboration has to be much earlier and much closer,” Smith observed. “You have to be much more open about the challenges that we’re facing either in EDA or IP or semiconductor or lithography or whatever. The companies definitely have to be more open and share the issues and resolve problems together. That’s the only way we’re going to move forward. It’s no longer a case that you can just supply, for example, a design rule manual from the foundry and then EDA guys say, ‘OK, we’ll implement that in software.’ They have to be done in parallel. We’ve seen that in the last two or three generations. I think the same is true here. What used to be a fairly simple, what kind of package do you want to use? Which foundry are you going to use? Put the two together and it’s going to work. No, no. Three partners or four, five, six are going to have to work together on a particular design now. And that’s how we learn.”

CEA-Leti’s Jerraya said that where EDA will play a strong role is in this relationship between the different partners of the 3D supply chain, because tuning the process will be a little bit more difficult than a SiP or PCB process, and the modeling and simulation and estimation of platform buses will be very important. In fact, so will all levels in the planning, the design, and the packaging.

“The OSAT and design houses probably will exchange some data and share some tools, and they will need some standards,” Jerraya said. “This puts strong pressure on EDA.”

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