The Top Five Trends in Verification to Watch for at DAC 2016

The Design Automation Conference in Austin is upon us, so it’s time for my annual preview of what to look for. In my mind, five trends stand out and are clearly visible in the DAC program as well as in what we are presenting at our booth:

1. Stronger ties between verification engines
2. Software-driven verification with portable stimulus
3. Metric-driven verification
4. Application specificity
5. Verification ecosystems

Looking at the ties between verification engines, for years users have been presented with different options to drive verification. The three dynamic engines of software-based simulation, emulation and FPGA-based prototyping were complemented with the static engines of formal verification. Software-based simulation extends from signal-based verification at the register-transfer level (RTL) to verification using transaction-level models (TLM) into the space of TLM-based virtual platforms for software development and software-driven verification. These engines are growing closer together, as I had previously written in “Top 15 Integrating Points in the Continuum of Verification Engines.” Cadence led the way back in 2011 with the introduction of the System Development Suite. Since then, the other two big vendors have followed with their own versions of connected engines, and at DAC in Austin you will see the debate about integration points in full swing. You can check out the different solutions on the floor at DAC and we have also organized a lunch panel “Seamlessly Connected Verification Engines? What Does It Take?” on Monday, moderated by Brian Fuller, featuring Cadence’s  Mike Stellfox, AMD’s Alex Starr, NVIDIA’s Narendra Konda and Jim Hogan. Yours truly also will be on a panel with AMD, IBM, Mentor and OneSpin on Tuesday afternoon, called The Great Simulation/Emulation Faceoff. That sounds like fun, doesn’t it?

Software-driven verification and portable stimulus have been hot topics in the industry for a while now, the latter driven by a working group in Accellera that will present a tutorial on Monday. The premise here is to be able to make verification re-usable between the above mentioned connected engines, and the best way to do that is to simply run verification on software on the processors that are used in the design anyway. This way, tests can be re-used from virtual platforms through simulation, emulation, FPGA-based prototyping and even the actual chip. This will for sure become a topic on the Monday panel that I mentioned, but you can also visit our DAC theatre and listen to Microsemi’s experience of using portable stimulus generated by our offering in this space. Other aspects of software will be presented by STMicroelectronics, who will discuss their experience using Indago ESWD for hardware/software debug. Check out the latest theatre schedule here.

Metric-driven verification always makes my German genes happy, as it creates order and allows us to collect, aggregate and connect the results of all the verification engines in one environment. Visit us at our booth to discuss how to, for example, merge and aggregate coverage data coming from simulation and emulation.

Application specificity will be visible all over DAC. This year’s focal topic – the Internet of Things (IoT) – is not an application domain per se, but spans across automotive, medical, industrial, mil/aero, mobile, networking and server spaces. At our Expert Bar, as well as in our Verification Experience Room at the booth, we invite you to look more at what we are doing in application-specific spaces.

Finally, ecosystems are key to success. No vendor really can do it all alone – as I had written recently in “Stories From The Village Called Hardware-Assisted Development” – so at our booth we will talk more about our partnership with ARM enabling mobile, server and IoT designs, and ARM will talk about models and how they work with Cadence tools in our DAC theatre. We will have Agnisys and Vayavya talk about their activities around register definitions and hardware/software interfaces in the context of portable stimulus for software-driven verification. AMLogic and AMD will present on their use of the core engines, Palladium emulation platform and Protium FPGA-based prototyping. They will be complemented by our eco-system partner Teledyne LeCroy, who will talk about their PCIe solutions in the ecosystem of connections for our hardware-based verification.

All in all, this DAC again shapes up as a great event to see the latest activities. See you in Austin!