The Week In Review: Design

Tools & IP
Synopsys added machine learning capabilities to its Design Platform. The company highlighted benefits to the PrimeTime signoff tool, which saw 5X faster power recovery in customer designs at leading-edge geometries. Renesas is using the tool, noting a 4X power ECO speed-up.

ArterisIP unveiled a standalone last level cache (LLC) for high-performance SoCs. CodaCache can be added to any AXI bus in an SoC design and be partitioned such that some or all of its RAM can be used as a Scratchpad. Size and organization is configurable at design and runtime. Target applications include ADAS, AI, data center processing, and networking.

eSilicon launched neuASIC, a platform for designing deep learning ASICs. The platform provides targeted IP offered in 7nm FinFET technology and a library of AI-targeted functions for creating custom accelerators. eSilicon says the platform can allow for earlier PPA analysis of various candidate architectures and is capable of handling changing AI algorithms.

PLDA uncorked PCIe 5.0 Controller IP supporting rev. 0.7 (32 GT/s) of the specification. The IP is available for ASIC, SoC and FPGA implementation and includes built-in Reliability/Availability/Serviceability (RAS) features for mission-critical SoCs.

Avery Design Systems updated its PCIe 5.0 and PIPE 5.1 VIP solution to support 32 GT/s speed, Equalization updates, PIPE 5.1 widths and frequencies up to 64 bits and 4000 MHz, and Precoding.

Mentor launched a tool focused on the creation of in-vehicle Controller Area Network (CAN) communications networks based on SAE J1939, a standard used for in-vehicle communications and diagnostics in heavy-duty commercial vehicles. Capital Systems Networks uses a single environment for network and electrical design and supports a generative design process.

Numbers
SoftBank is selling 51% of its stake in Arm Technology China to a consortium of Chinese investors, which will form a joint venture for licensing Arm’s IP in China. Arm will continue to receive a significant proportion of all license, royalty, software and services revenues, according to SoftBank. Arm will continue to develop the source code for all processors outside of China, however, according to a company spokesman. Softbank disclosed the deal last year.

AI chip startup Hailo completed a $12.5 million Series A funding round. Hailo is building a deep learning chip for edge devices, particularly automotive as a target market, with an expected release of H1 2019. Investors include Ourcrowd.com, Maniv Mobility, and Next Gear Ventures; as well as angel investors, Hailo Chairman Zohar Zisapel and Delek Motors CEO Gil Agmon.

Standards
IEEE is forming two new study groups to focus on the 802.11 standard as it relates to vehicular environments and broadcast services. The Broadcast Services (BCS) group focus is on simultaneously broadcasting local information over IEEE 802.11 WLAN without recipients needing to actively connect to an access point, while the Next Generation V2X (NGV) group is considering vehicles’ requirements for higher throughput, improved reliability and efficiency, and/or extended range.

Events
DAC 2018: June 24-28 in San Francisco, CA. The design automation conference and exhibition is adding a cloud-focused Infrastructure Alley to the floor this year. Keynotes will discuss issues of connected products and ambient intelligence, state-of-the art computing for AI, RISC-V, and socially assistive robotics.