The Week In Review: Design

Synopsys adds hybrid verification platform; Mentor introduces new embedded hypervisor; NXP inks deal with Delphi for vehicle-to-vehicle chips; TSMC certifies Mentor, Synopsys tops for 16nm.


Synopsys rolled out a hybrid verification platform, which it said can shave months off design time. The platform acts like a bridge between emulation, FPGA prototyping, simulation, static and formal verification and debug.

Mentor Graphics uncorked a new version of its embedded hypervisor, which includes better system configuration, debugging and hardware support. The hypervisor is aimed at a slew of vertical markets ranging from medical to automotive and consumer electronics. Hypervisors are becoming increasingly important for security, as well as a way of utilizing multiple cores more effectively.

Mentor Graphics rolled out embedded Linux software for AMD‘s embedded G-Series SoCs and APUs.

NXP signed a deal with Delphi Automotive for its vehicle-to-vehicle and vehicle-to-infrastructure chipset. The chips communicate alerts from other cars and infrastructure about hazards, including those that aren’t visible by the driver.

TSMC certified Mentor‘s analog FastSPICE platform and Synopsyscustom and digital design tools for its 16nm finFET version 0.9 process. TSMC expects to roll out version 1.0 of that process technology by November. TSMC also inked a deal with Synopsys for 10nm finFET collaboration.

ARM‘s TechCon will kick off this week at the Santa Clara Convention Center, beginning Wednesday, Oct. 1.

Atrenta said it would host its first user conference on Oct. 8 at Levi’s Stadium in Santa Clara.

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