The Week In Review: Design

Deals

Kilopass extended its deal with ICScape, which makes a Parallel SPICE simulator, for eNVM IP at advanced finFET nodes. Kilopass has been working with ICScape for the past couple of years as part of its qualification methodology.

IP

Silvaco released three MIPI I3C sensor controller IP cores. Developed with NXP to push adoption of I3C, the new products are an Advanced Slave core with optional I3C features and power management capabilities, a Dual Role Master core that incorporates master mode functionality, and an Autonomous Slave core, which includes the ability provide I3C capabilities to simple sensors without a microprocessor.

Arasan uncorked its new MIPI C-PHY IP Core. The universal PHY can be configured as a transmitter, receiver or both and is fully compliant with the C-PHY specification Version 1.1 while also being compliant to the D-PHY 1.2 Specification.

QuickLogic will license its embedded FPGA technology for designs on GlobalFoundries’ new power optimized 22nm FDSOI process, scheduled for production in 2017. The company also plans to introduce design tools to evaluate, target and define custom eFPGA logic cell array sizes and generate the necessary design files. The IP is currently available for 65nm and 40nm processes.

Uniquify announced LPDDR4 Super Combo IP for the 28nm low-power process node from several unnamed foundries. The IP offers up to 3200Mbps per pin performance for mobile LPDDR4 DRAM and has a flexible configuration to support other DDR combinations.

Open-Source

SiFive launched its first RISC-V SoC, FE310, along with a low-cost development board. Targeted at microcontroller, embedded, IoT and wearable applications, it was fabricated in TSMC 180nm and includes a 32-bit RV32IMAC core running at 320+ MHz. The company contributed the RTL code to the open-source community.

BaySand, Codasip, Codeplay and UltraSoC partnered on an integrated IoT development platform based on the RISC-V ISA. The project incorporates BaySand’s foundational IP and Metal Configurable Standard Cell technology, Codasip’s extensible RISC-V-compliant processor implementation, Codeplay’s software development tools for open standards middleware, and UltraSoC’s on-chip debug and analytics architecture.

Certifications

Toyota approved Mentor Graphics’ Volcano VSTAR AUTOSAR basic software stack for use in all Toyota vehicles. The software stack provides scalable AUTOSAR 4 middleware which abstracts the application from the hardware-dependent layer.

Numbers

Synopsys released financial results for the fourth quarter of 2016 with revenue of $633.7 million, up 7.9% from the same period last year. Revenue for the entire fiscal year was $2.42 billion, an increase of 8% from FY2015. On a GAAP basis, net income per share stood at $0.47, up 51.6% from $0.31 per share in Q4 2015. Non-GAAP income per share for the quarter was $0.77, up 14.9% from $0.67 per share in Q4 2015. For the year, GAAP income was $1.73 per share, up 21% from $1.43 per share in the last financial year, while non-GAAP income per share was $3.02, up 9% from $2.77 per share in FY2015.

Synopsys also finalized its acquisition of security services provider Cigital and its spinout security tool company Codiscope.

Related Stories
System Bits: Nov. 29
300mm quantum demo; photonic crystals; IoT device biosignal measuring.
Formal’s Roadmap
Experts at the Table, part 2: The need for a formal specification, coverage and progress toward formal verification for analog.
Homogeneous And Heterogeneous Computing Collide
Part one in a series. Processing architectures continue to become more complex, but is the software industry getting left behind? Who will help them utilize the hardware being created?