The Week In Review: Design

MIPS up for sale; AMS simulation; thermal simulation; neural network IP.


Imagination has put the MIPS embedded processor and Ensigma mobile connectivity groups up for sale, refocusing on graphics after last month’s announcement that Apple would no longer use the company’s GPU IP. Imagination also began formal dispute resolution procedures with Apple.


Synopsys released new versions of its HSPICE, FineSim and CustomSim circuit simulation products, adding new Monte Carlo-based variability analysis, advanced reliability analysis capabilities, and improved SPICE performance for finFET designs.

Mentor released the latest version of its FloTHERM XT electronics cooling software. New capabilities include simulation of spinning parts in electronic enclosures; temperature-dependent power simulation; enhanced “Design of Experiments” parametric studies functionality to determine best design coverage; and thermal territory simulation when using various component materials.

Aldec launched its new Xilinx Zynq-based TySOM-2A-7Z030 Embedded Prototyping Board. The board is designed to ensure flexibility in selecting peripherals, has 250 I/O and 4 GTX transceivers, hosts an onboard FMC-HPC connector, and features a combination of memories (1 GB DDR3, SPI flash memory, EEPROM, uSD), communication interfaces (2× Gigabit Ethernet, 4× USB 2.0, UART-via-USB, Wi-Fi, Bluetooth, HDMI 1.4), and other miscellaneous modules (LEDs, DIP switches, XADC, RTC, accelerometer, temperature sensor).


Cadence unveiled a standalone, self-contained neural network DSP IP core optimized for vision, radar/lidar and fused-sensor applications. The Vision C5 DSP offers 1 Tera MAC (TMAC)/sec computational capacity to run all neural network computational tasks (convolution, fully connected, pooling and normalization) on less than 1mm2 silicon area. According to Cadence, the DSP is up to 6X faster in the AlexNet CNN performance benchmark and up to 9X faster in the Inception V3 CNN performance benchmark compared to commercially available GPUs.

VeriSilicon launched a highly scalable and programmable processor for computer vision and artificial intelligence. It provides over 3 TMACs per second, with power consumption more efficient than 1.5 GMAC/second/mW on 16FF process technology. The IP consists of a highly multi-threaded Parallel Processing Unit, Neural Network Unit and Universal Storage Cache Unit.

Synopsys launched VIP and a source code test suite for MIPI CSI-2 v2.0, MIPI D-PHY v2.1, MIPI C-PHY v1.2, and MIPI M-PHY v4.1. The VIP uses a Native SystemVerilog/UVM-based architecture and features error injection capabilities, built-in-protocol checks, coverage, and verification plans.

Cadence revealed its interface and verification IP for Cache Coherent Interconnect for Accelerators (CCIX), an open chip-to-chip interconnect standard for datacenter servers. The integrated solution, based on the PCIe 4.0 specification, includes controller, PHY, software drivers, scripts for design and verification, simulation models and user guides. The entire package is pre-verified using Cadence verification IP for CCIX.

InfoSec Global and Synopsys collaborated on an embedded Root of Trust solution that integrates InfoSec Global’s Agile Cryptography capabilities with Synopsys’ DesignWare tRoot Hardware Secure Module, providing programming interfaces to customize secure industrial IoT SoCs. The platform allows for the creation of secure channels for remote device management and real-time updates to cryptography on chipsets in the field.


Mentor’s Nucleus RTOS now supports the ARM Cortex-A72 processor based on the 64-bit ARMv8-A architecture, and NXP’s LS1046A SoC. The reference implementation on the NXP LS1046A-RDB board includes device support for UART and Ethernet.

Microsemi extended an OEM agreement that enables the company to integrate Synopsys’ FPGA synthesis tools with a customized tool suite used with Microsemi FPGAs.

jNet ThingX’s JavaCard/GlobalPlatform OS has been ported and optimized for Synopsys’ DesignWare ARC SEM security processors. It supports Common Criteria certification up to Evaluation Assurance Level 5+ and is targeted at NFC payment, government documents/IDs, smart cards, smart meters and over-the-air provisioning.

People & Events

Janet Olson, vice president of engineering for RTL Synthesis R&D at Synopsys, has been selected as the recipient of the Marie R. Pistilli Women in Engineering Achievement Award for 2017. Olson is named as the co-inventor on three U.S. patents and has four patents pending for DFT synthesis technology and novel RTL synthesis techniques. Olson also participates in diversity panels and recruiting events for women in engineering, and she actively mentors emerging talent in the EDA industry.

Registration has opened for MPSoC 2017, a conference focused on multicore and multiprocessor hardware and software systems plus software-defined hardware for energy-efficient and high-performance computing. The forum will be held July 2-7 2017 at the Les Trésoms Hotel in Annecy, France. Early registration closes May 15.


The Khronos Group released the OpenVX 1.2 specification for cross-platform acceleration of computer vision applications and libraries. OpenVX is a high-level, graph-based API targeted at real-time mobile and embedded platforms. New functionality includes neural network acceleration, feature detection, image classification, and conditional graph processing. Khronos also released a modification of OpenVX 1.1 specification targeted at safety critical systems, OpenVX SC.


Ansys reported financial results for the first quarter of 2017 with revenue of $253.4 million, up 12% from the first quarter of 2016. On a GAAP basis, earnings per share for the quarter were $0.73, up 16% from $0.63 in Q1 2016, while non-GAAP earnings were $0.89 per share, also up 16% from the previous quarter’s $0.77. For the second quarter, the company expects revenue in the range of $253.6 – $262.6 million.