The Week In Review: Design

Tools

Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It supports line, branch, statement and (soon) expression coverage. The C-to-RTL-Equivalence SLEC (sequential logic equivalence checking) HLS tool formally verifies C++/SystemC source to Catapult-synthesized RTL and employs a coverage methodology that highlights which code still needs to be tested if a full proof could not be achieved. Additionally, Catapult HLS now can generate a complete UVM environment for synthesized RTL.

New EDA entrant Baum announced it will launch a state-of-the-art, high-speed and accurate power analysis and modeling solution to be used earlier in the design cycle. It will support dynamic and static power, taking in RTL and netlist descriptions of the design and initially target the automotive, IoT, mobile, networking and server markets. The launch is planned for September.

Ansys updated its family of simulation tools for electronics. For power noise and reliability sign-off, RedHawk-SC added an elastic compute engine, which uses commodity computers in private or public cloud environments, and gives a 10x improvement in capacity and scalability architecture over previous releases of RedHawk. Path-FX supports users with on-chip variability analyses and integrates with RedHawk-SC to provide comprehensive timing and voltage variability analysis, while CMA lets designers model and analyze power integrity and signal integrity effects with chip power models produced by RedHawk-SC.

Mentor released a High-Density Advanced Packaging (HDAP) flow for advanced IC package design. The flow introduces a graphical, rapid virtual prototyping environment which explores and integrates heterogeneous ICs with interposers, packages and PCBs, as well as a complete HDAP design-to-mask-ready GDS output solution to manages the physical implementation of the package. It is integrated with HyperLynx technologies for 3D signal integrity and power integrity, and in-process DRC. Calibre 3DSTACK provides 2.5D/3D package physical verification.

Plunify launched a new FPGA tool that recommends RTL code fixes based on timing path and RTL code analysis. It reads critical-path information and pinpoints corresponding source code segments, analyzes them and then proposes RTL fixes. Additionally, Plunify updated its InTime timing closure and performance optimization tool for FPGAs, including an Auto Placement feature that supports Quartus Prime Pro 17.0, Quartus 17.0, and Vivado 2017.1.

IP

Synopsys uncorked a complete CCIX IP solution, consisting of controller, PHY and verification IP delivering data transfer speeds up to 25Gbps and supporting cache-coherency for high-performance cloud computing applications. The IP is built on Synopsys’ PCI Express 4.0 architecture and offers data protection and integrity in the datapath and RAM.

Avery Design Systems debuted several new verification IP solutions, including the CCIX, major updates to the company’s flagship PCIe 4.0 VIP for CCIX over PCIe and PCI-SIG v0.9 snapshot draft specification, and ARM AMBA 5 CHI VIP. The The CCIX VIP consists of CCIX home agent model incorporating configurable number of request and slave agents, interconnect, and directory agents, protocol checking, snoop response verification, performance measures, and functional coverage.

PLDA released a Plug & Play PCIe 4.0 host platform with built-in PCIe traffic monitoring, enabling link-training and link performance analysis. The analyzer provides the ability to validate interoperability and to measure the PCIe bandwidth performance of applications.

Mellanox and Synopsys teamed up to demonstrate full system interoperability between their two independently developed PCIe 4.0 solutions. The host, including the DesignWare Root Complex IP for PCIe 4.0 specification, executes full initialization across the PCIe link at 16 GT/s with the Mellanox ConnectX-5 Ethernet and InfiniBand network adapter.

Synopsys expanded a suite of free and open source software and tools for ARC processors. The release adds support for the latest ARC SEM and ARC HS processors, and an OpenThread protocol implementation for the development of digital home applications, as well as support for ARC Software Development Platforms. The suite is available at embARC.org.

Uniquify’s LPDDR4 Super Combo IP for the 28nm low-power semiconductor process node is in volume production. It provides up to 3200 Mbps per pin performance for mobile LPDDR4 DRAM. The subsystem includes controller, PHY and I/O components. A flexible configuration supports other DDR combinations, such as DDR3/4 and LPDDR2/3.

Standards

PCI-SIG announced 32GT/s as the next progression in speed for the PCIe 5.0. Slated for completion in 2019, the specification development is underway with Revision 0.3 already available to PCI-SIG member companies. For high-end networking like 400Gb Ethernet solutions and dual 200Gb/s InfiniBand, the PCIe 5.0 architecture operates at full duplex and provides up to 128GB/s in bandwidth.

Deals

Rambus will provide Synopsys with its CryptoManager infrastructure and key provisioning services to support Synopsys’ tRoot Hardware Secure Modules (HSMs) with Root of Trust, enabling secure remote lifecycle management of connected devices.

STMicroelectronics selected Synopsys VC Formal as their formal verification solution for advanced microcontroller designs. ST cited the ability to locate corner case bugs earlier in the design cycle, achieving faster and earlier verification closure.

Stream TV Networks utilized Mentor’s Catapult HLS tool to create an IP block that converts 2D or stereo-3D video content to the Ultra-D format for glasses-free 3D digital displays.