The Week In Review: Design

Synopsys buys materials modeling company; security subsystem; DDR5; neural network accelerator.

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M&A
Synopsys acquired materials modeling company QuantumWise. QuantumWise tools focus on atomic-scale modeling of nanostructures using quantum-mechanical computational methods, classical potentials, and electrostatic models. Based in Denmark, the company was started in 2008 when it acquired the assets of Atomistix. The technology will be integrated with Synopsys’ Sentaurus TCAD. Terms of the deal were not disclosed.

IP
Synopsys debuted an integrated, pre-verified hardware and software SoC environment targeted at high-value embedded applications such as embedded SIMs, smart metering and embedded Universal Integrated Circuit Cards. The ARC Secure IP Subsystem contains an ARC SEM110 or SEM120D Security Processor with SecureShield to protect against side-channel attacks and includes both software- and hardware-accelerated cryptography options as well as secure instruction and data memory controllers.

Rambus completed a DDR server DIMM buffer chipset prototype for DDR5 memory technology. Rambus’ Luc Seraphin expects the main drivers of DDR5 adoption to be data-intensive applications such as big data analytics and machine learning.

Imagination uncorked a standalone hardware IP neural network accelerator. PowerVR 2NX supports fully flexible bit depth for weights and data including low bandwidth modes down to 4-bit and 2048 MACs/cycle in a single core, with the ability to go to higher levels with multi core. According to the company, it has lower power and bandwidth than its competitors.

Synopsys launched an IoT Development Kit that includes a silicon implementation of the ARC Data Fusion IP Subsystem as well as a set of peripherals commonly used in IoT designs such as USB, I3C and PWM. Pre-verified software for the kit includes drivers, FreeRTOS, and middleware, plus a programming environment including optimized compiler, debugger, and libraries.

Imagination launched a new generation of PowerVR GPUs. The Series9XE GPUs have a new eight pixel/clock core for GUI focused applications requiring support for 4K60, while the Series9XM GPUs sport increased compute density. Both lines reduce bandwidth by up to 25% over previous generations.

Certifications
Mentor’s Calibre and Analog FastSPICE tools have been certified for Intel’s 22nm FinFET low power (22FFL) process.

Ansys‘ electromigration, power and electrostatic discharge tools were certified for Intel’s 22FFL process.

Cadence’s digital and signoff tools and custom/analog tools were certified for Intel’s 22FFL process, along with a full flow available to Intel Custom Foundry customers.

Synopsys‘ design platform was certified for Intel’s 22FFL process. The company also released a digital reference flow for the process.

Synopsys’ design platform, including IC Compiler II, IC Validator, PrimeTime, and StarRC tools, was certified for GlobalFoundries‘ 22nm FD-SOI (22FDX) process technology.

Additionally, Synopsys announced IP, including PHYs for USB 3.1/3.0/2.0, USB-C 3.1/DisplayPort, PCI Express 3.1/2.0 and HDMI 2.0 TX, as well as data converters, for the 22FDX process.

Deals
NXP licensed additional uses of ArterisIP’s Ncore cache coherent interconnect IP and functional safety Ncore Resilience Packages for use in automotive applications.

Brite Semiconductor, SMIC, and Synopsys teamed up on an IoT platform based on Synopsys’ ARC Data Fusion IP Subsystem and interface IP, implemented by Brite’s design services for SMIC’s 55nm ultra-low power process. A test chip showed up to 45% reduction in dynamic power and 70% reduction in leakage power compared to SMIC’s 55LL process.

Events
Decoding Formal: Sept. 26, 11:30am – 4pm in San Jose, CA. The quarterly event for formal verification includes presentations from Arm’s Vikram Khosa on deployment of sign-off formal and from ArterisIP’s Chirag Gandhi on formal and cache coherent protocols. Additionally, origami artist and applied physicist Dr. Robert J. Lang will speak on the mathematical principles behind the art and science of origami. The event will be held at Oski Technology’s new headquarters.

ARC Processor Summit: Sept. 26 in Santa Clara, CA. Opening with a keynote by Jeff Bier of the Embedded Vision Alliance and BDTI on how AI and machine learning are transforming electronic products, the day features concurrent tracks dedicated to hardware, software, and embedded vision.

Arm TechCon: Oct. 24-26 in Santa Clara, CA. The Arm ecosystem-focused conference features a number of keynotes from Arm on subjects from the value of IoT data to state-of-the-art silicon process technologies. Invited speakers Stacey Higginbotham, Mary Aiken, and Jessica Barker will discuss the key challenges facing IoT and why a more human-centered approach is needed when designing security.