The Week In Review: Design/IoT

Marie R. Pistilli nominations open; Cadence’s new test tool and Imagination flow; Synopsys circuit simulator update; Aldec lifecycle management; ARM IP for UMC; USB 10 Gbps and SAS 24G; automotive Ethernet; Cadence & NXP Q4 results.



DAC is now accepting nominations for the Marie R. Pistilli Women in EDA Achievement Award, which recognizes individuals who have visibly helped to advance the profile of women in the EDA industry. Nominations must be received by March 3rd.


Cadence unveiled its new Modus Test Solution, which the company says enables design engineers to achieve an up to 3X reduction in test time. The tool incorporates patent-pending, physically aware 2D Elastic Compression architecture that enables compression ratios beyond 400X without impacting design size or routing.

Cadence also announced a complete digital and signoff reference flow for Imagination’s PowerVR Series7 GPUs. According to Cadence, the full synthesis and implementation of 5.5M instances was completed in 2.5 days, providing more than a 2X turnaround time improvement in comparison with the company’s previous design flows.

The latest update to Synopsys’ circuit simulators includes a native environment for simulation management and analysis, adding full access to the features available in Synopsys SPICE and FastSPICE simulators in the company’s HSPICE, FineSim and CustomSim products.

Aldec updated its requirements lifecycle management solution for FPGAs/SoCs, Spec-TRACER 2015.12. The latest release adds additional features and capabilities for systematically managing Validation and Verification data and artifacts of large and complex FPGA/SoC DO-254 projects.


ARM uncorked its physical IP platform and POP IP for UMC’s 28HPCU, the foundry’s second-generation High-K/Metal Gate 28nm process. The platform includes standard cell libraries and memory compilers and POP technology for the Cortex-A53 and Cortex-A7 processors.

Synopsys achieved SuperSpeed USB 10 Gbps (USB 3.1 Gen 2) IP certification from USB-IF, with PHYs consuming less than 50 mW power at 10 Gbps speeds in 14/16-nm FinFET process technologies.

Synopsys also released verification IP to support the Serial-attached SCSI (SAS) 24G standard. The VIP uses a SystemVerilog, UVM-compliant interface, is capable of switching speed configurations dynamically at run time and includes an extensive and customizable set of frame generation and error injection capabilities.

IoT & Automotive

Marvell introduced a new automotive Ethernet reference platform integrated with TE Connectivity’s MATEnet modular and scalable connector for automotive Ethernet. The development platform supports audio video bridging switching solutions with 100BASE-T1 and 1000BASE-T1 Ethernet PHY capability.


Cadence released fourth quarter results with revenue of $441 million, up 4.3% from Q4 2014. Revenue for 2015 totaled $1.702 billion, up 7.7% from last year’s total. Net income for the year stood at $0.81 per share, up 56% on a GAAP basis. Non-GAAP, income was $1.09 per share, up 16%. CFO Geoff Ribar highlighted a 17% growth in the company’s IP business.

NXP also reported financial results. Q4 revenue was $1.61 billion, up 4% year-on-year. The whole year gave revenues of $6.1 billion, up 8% from 2014, including the benefit of approximately one month of revenue contribution from Freescale. For 2015 GAAP earnings per share were $6.10, a 181.1% increase over 2014, with non-GAAP EPS standing at $5.60, up 17.6%.

NXP’s antenna R&D center in Chandler, Arizona, USA, is hiring with a focus on candidates with radio frequency expertise especially in RF medium power and RF WLAN competency.

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