The Week In Review: Design/IoT

Tools

Synopsys unveiled a new custom design solution targeting FinFET layout, introducing visually-assisted routing automation, a built-in design rule checking engine, templates to apply previous layout decisions to new designs, and IC Compiler integration. TSMC certified the new tool for 10nm and 7nm FinFET process technologies. It has also been adopted by STMicroelectronics, GSI Technology, and Asahi Kasei Microdevices.

Synopsys also released a new lint tool incorporating advanced structural techniques, a new hierarchical engine and deeper functional analysis which the company says gives 10X faster performance, 5X improvement in memory footprint and 3X faster design closure.

Ansys introduced a new licensing model that provides hourly-based access to the company’s simulation portfolio, allowing for peak usage on top of more traditional licenses and flexibility for short-term projects.

Associations, Events & Standards

The EDA Consortium changed its name to the Electronic System Design Alliance. More importantly, it broadened the group’s charter to include IP and an increased focus on software development alongside its traditional EDA roots.

Curious about this year’s DAC keynotes and SKY talks? They’ve been revealed.

JEDEC released two standards: JESD243, which identifies commercial best practices for mitigating/avoiding counterfeit monolithic microcircuits, hybrid microcircuits and discrete semiconductor products, and JESD220-2 for Universal Flash Storage to provide a removable storage solution while maintaining sequential and random IOPs performance for future mobile markets. Both are available for free download.

Chips

Marvell announced a 28nm mainstream printer SoC, integrating a dual-core Cortex-A53 processor running at 1.0GHz, dual-channel configurable scan and print pipelines, a high-performance 2D/3D GPU, and an integrated GE Ethernet MAC and PHY.

Deals & Certifications

Movidius licensed Arteris’ FlexNoC IP for use in its machine learning vision processing units, highlighting ultra-low power consumption and advanced simulation/architectural exploration features as reasons for selecting the IP.

Andes Technology achieved 10,000 installations globally of its AndeSight Eclipse-based integrated development environment.

Cadence’s complete suite of digital and signoff tools were certified for Samsung Foundry’s PDK and foundation library for the 14LPP process.

Intel Custom Foundry certified Synopsys’ digital and signoff implementation tools for the 10nm tri-gate process technology.