The Threat Within

There are 10 billion vias between metal layers in a chip, and one via defect can render the entire chip useless.


By Connie Duncan
Given that today’s advanced chips can contain billions of transistors, 60 miles of copper wiring and 10 billion vertical connections between metal layers, the challenges and potential pitfalls this level of complexity presents are mind-boggling. One major problem on the horizon at 20nm and below is the threat of voids forming in the vertical interconnects commonly called vias.

Provided below are two charts that NVIDIA‘s John Chen presented at the 2011 IMEC Technology Forum to illustrate how one via defect can render an entire chip useless. The charts below demonstrate that as chip features scale down in size, the use of single vias between metal layers is increasing. Historically, to ensure chip reliability and yield, chipmakers build in redundancy with multiple vias, meaning that electrons can take more than one path between two points on a chip. But with the intense competition for real estate on a die and to keep die sizes from getting much larger, single vias are becoming more prevalent.

The risk of single via dependency is that it leaves no margin for error —any defect in the millions of single vias on a chip can render it useless. The second graph details this threat. It shows that as chip features scale, defects in a via can result in significant yield loss. Projecting to 20nm, defect level needs to be <1 DPPB, that is fewer than one defect in every billion vias. If that specification isn’t met, makers of advanced ICs risk a stunning 30% yield loss.

With Applied’s recently announced Endura Amber PVD system, this scenario has been re-written—eliminating voiding by “reflowing” copper down into the bottom of the via from the top where hole size openings as small as 200 atoms across are prone to narrowing. By opening the narrow region that can pinch off the via structure, and flowing copper into the via from the bottom up, the new system allows perfect, completely filled structures, making a zero-defect rate possible for the first time, resulting in high reliability and yield.

Chart Source: NVIDIA Corporation 2011

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