Time To Market Concerns Worsen

Time to market has always been an issue for chipmakers in highly competitive sectors, but as complexity of chips continues to grow at advanced nodes, and as markets shift increasingly toward consumer electronics, it has jumped to the No. 1 concern.

Interviews with engineers at multiple levels inside of some of the largest and midsize chipmakers, conducted by Semiconductor Engineering over the past two months, have confirmed that time-to-market has taken on a new sense of urgency across the supply chain. Those engineers attribute this to a number of factors, including:

• As large OEMs such as Apple, Google and Amazon focus on making their own chips, the remaining opportunities are becoming more competitive. Getting to market first can mean the difference between recouping an increasing NRE investment or losing all of it.
• The number of changes to designs is now continuous at advanced nodes, in part because the processes and tools are not fully baked by the time the designs begin, and in part because the increasing focus on consumer markets means that requirements change so quickly.
• There are far more features and IP blocks that need to be integrated into designs, as well as more physical effects that need to be considered. And while EDA tools are keeping pace with complexity, the volume of issues that need to be dealt with is rising considerably.
• There is more uncertainty involving lithography, new transistor structures, yield and emerging materials at the most advanced nodes, which could take longer to process by foundries—a factor that particularly affects midsize companies and even large companies with limited run production.

EDA vendors have been watching these changes for some time. Mentor Graphics recently commissioned a Wilson Research Group study that shows designs are about 10% ahead of schedule compared with previous years when the study was done. But while those statistics look rosy on the surface, there’s more than meets the eye.

“We’re also getting anecdotal data that would lead you to different conclusions,” said Wally Rhines, Mentor’s chairman and CEO. “If you look at all the things that are being done in design these days, the list has tripled over the last five years. We’re now dealing with power management checks and more verification. The overall task has increased.”

Rhines said that while companies are delivering chips on time, it requires more effort per design. Moreover, what used to be a sequential process is now a complex matrix that involves everything from software prototyping to a series of constant updates.

What’s changed?
Unlike in the past, when chipmakers accused EDA vendors of not keeping pace with volumes of data and failing to update their verification technology, the bulk of the blame is no longer directed at the tool makers. There are still complaints about the need for better pathfinding solutions to do what-if analysis and tradeoffs and vendor-specific problems. But the real challenge that has to be met to keep on schedule is dealing with the volume of everything—more features, more changes, along with horizontal challenges such as low power, and security, which will become particularly important for IoT applications. Keeping on schedule is getting harder.

“The real problem is that it’s becoming harder to predict and nail down a schedule because there are too many surprises,” said Mike Gianfagna, vice president of marketing at eSilicon. “So you do another two or three netlist drops, then you close timing, and then you get new versions of IP and the regression breaks. The root cause is unexpected design surprises. So you may expect your IP to break two times, but what happens if it breaks five times. That kind of stuff is showing up at advanced nodes in particular, and it’s clos to impossible to predict everything. You may get a new PDK from the foundry to fix the stability of a process, or you may see big differences in IP quality from one vendor to the next. Right now, there is no ‘Good Housekeeping Seal of Approval’ for IP.’

There is almost universal recognition of this problem among chipmakers, design services companies, and EDA companies.

“It’s not that it’s more important than it was before,” said Hans Bouwmeester, director of IP at Open-Silicon. “But there are more pieces to the puzzle than ever before. It’s hard to get to the point where you can hit a window and forecast it correctly, which is why we’re seeing time-to-market issues now. On top of that, the stakes are higher. Mask costs and NRE are higher, and it takes more to recoup your investment. At 14nm, the amount of time it takes to complete a chip is increasing with double patterning, which increases fab time. EDA time is increasing due to double patterning, too. You have to take more electrical behavior into account, which means more simulation, more timing closure.”

Thinking differently about designs
The problem is that not all of this can be done consecutively like passing a baton from one group, such as place and route, to another, such as RTL coding and then onto verification and then to software development. It all has to be started simultaneously—and tweaked simultaneously.

“The challenge we’re seeing is that chip companies are being forced to start a project before all the requirements are known,” said Randy Smith, vice president of marketing at Sonics. “This is all being driven by the push into the consumer space, where the first to market gets 70% of the market and the next to market gets the remaining 30%. Everyone else ends up with zero. That’s why we’re seeing a shift away from design costs being the number one priority. They’re still important, but they’re no longer top on the list.”

Smith said that what needs to be fixed isn’t the tools. It’s the methodology. That will drive new tool requirements. “So you need to configure the IP to support always-on, but in conjunction with a mostly dark silicon mentality. And you need to understand that the design will evolve until the time that it ships. Right now, the tools dictate the methodology based on what they’re able to do. We have to rethink that.”

Some of this varies greatly by vertical market. An automotive chip, for example, has a much different time-to-market window than a smart phone chip. But pressure is building in all areas.

“What we’re seeing is there’s a rush to get out first, perfect it, and then come back with a new chip in three months,” said Kurt Shuler, vice president of marketing at Arteris. “That’s easier in the mobile phone market, though than it is in other markets like home gateways, though, which is changing all the time. The only thing you can do there is make your best guess about where the market will be in six months or a year. You may have to deal with new requirements, or you may find there’s a big pricing change and you either have to stop building a chip altogether or remove certain features.”

He said the advantage of companies that churn out lots of chips is that they get good at it, which is why some of the bigger companies and some of the design services houses are pulling away from the rest of the pack right now. “We’re seeing this in China right now where there is a shakeout coming.”

Shifting roles
All of these problems are good for tools vendors, which have been benefiting handsomely from the sale of more powerful tools and hardware-assisted approaches such as emulation and FPGA prototyping. But even EDA vendors are struggling to come up with a better plan for how all of these steps can be integrated more effectively.

To some extent, that involves integrating the tools more tightly so that information can be passed back and forth more easily. The Big Three EDA vendors have trumpeted the benefits of fully integrated flows for the past decade, and for the most part all EDA tools—regardless of vendor—are tightly integrated into the flows supported by the major foundries and based upon the Big Three’s architectures.

But what’s also changed, particularly at advanced nodes, are the working relationships between companies and within companies. At 16/14nm, it’s the norm for chipmakers, foundries, EDA companies and major IP suppliers to work together on advanced designs—at the same time and often in the same place.

“We’ve been talking for awhile about a ‘Shift Left’ approach, where serial processes are being done in parallel,” said Steve Carlson, group director of marketing at Cadence. “We’re seeing the same thing at new nodes with collaboration. So DRM (design rule manual) version 0.9 is passed to EDA instead of version 1.0. We’re engaging three to five years ahead of production, developing PDKs and methodologies so that when we get to a new node offering we’ve already gone through a test chip and target architecture. It’s basically proof of concept, but it’s changing where the customer is getting involved. It’s four-way collaboration.”

That Shift Left approach applies not only to a single node. It applies to multiple nodes at once. Chipmakers, particularly in the consumer space, are working on designs at 10nm right now, even before shipping 16/14nm chips, and they are in early development on 7nm. It also applies to the development hardware and software simultaneously, which Carlson says is raising some eyebrows among design teams.

“People think about the parallelization of hardware and software as a way of being able to add new hardware features more easily, but what happens when you need a new driver?” asks Carlson. “You may need to write millions of lines of new code for the power feature to shut down a portion of the chip.”

So while companies are pushing for first-time silicon success—no re-spins—they’re spending far more time getting the software out the door. In the past this has been built into schedules, where large chipmakers take otherwise successful first-pass silicon and optimize it further into production chips. But that schedule is getting squeezed, forcing them to begin optimizing ahead of silicon.

“That optimization has to work across tool boundaries,” said Swami Venkat, senior director of marketing for the Galaxy Design Platform at Synopsys. “When you think about what does it really mean to reduce time, it’s fewer iterations, less time to quality improvement, and more what-if analysis that needs to be done while the RTL is getting cleaned up.”

Venkat noted that almost every large organization has cut down turnaround time by 10% to 30% using these approaches. “But you can’t reduce that beyond a certain limit.”

What else can be done?
Or at least you can’t reduce it using the same approaches. But there is still a fair amount of low-hanging fruit for reducing time to market. Design services companies have been quick to jump on new approaches to speeding up designs. Open-Silicon introduced a SerDes evaluation platform with pre-integrated IP, while eSilicon rolled out an online GDSII configuration tool that allows different pieces of IP to be swapped in and out for planning purposes. These are different approaches to what ARM CTO Mike Muller referred to as “bigger LEGOS” to simplify integration.

Another area for improvement is utilizing what’s already available. Metric-driven verification, for example, has been available for the past half-dozen years, but so far its adoption has been meager. “Best known-practices in verification are not fully deployed,” said Cadence’s Carlson. “And then on the IP and re-use side, companies may not have the expertise needed to get through all of the integration work.”

And finally, there are entirely new approaches under consideration, such as stacking die in 2.5D and 3D-IC configurations, as well as limiting the number of IP options and more reference platforms. So far there has been a lot of exploration in these area, but what will turn into high-volume production chips is still anyone’s guess.