Time To Think

We have entered a period of system-level financial analysis. Decisions being made now will have a big impact in the future.

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The semiconductor industry seems to be running place these days—maybe even sprinting in place.

At the leading edge of design, companies are still looking at the ramifications of moving to finFETs. The move to a 20nm process with double patterning on 16/14nm finFETs, depending on the foundry, looks like a fairly safe bet for those companies with the volume and the resources to design and debug them. But with EUV now likely to miss 10nm and maybe even 7nm, coupled with new materials for higher mobility of electrons, the cost of sticking on that road map is becoming a much more complex accounting question.

This may explain why both GlobalFoundries and TSMC are putting in place reference flows for stacked die—both 2.5D and full 3D—and companies are now talking more seriously about platform strategies that can span multiple nodes. And it may help to explain why so much work is being done at older process nodes, such as FD-SOI at 28nm with consideration of finFETs rolling backward to older nodes where the reduction in current leakage would allow higher clock frequencies.

The Internet of Things will be a huge opportunity for the semiconductor industry as a whole, but who will win in this space and how they ultimately take advantage of this market is a mystery. Will it be the platform makers who win? The makers of IP subsystems? Or will it be the more mundane industrial sensor market that takes the upper hand?

There are discussions about every aspect of these changes, and they reach deep in all directions. The semiconductor industry is nothing without an open-ended growth path, like the one Moore’s Law has provided since the mid-1960s, and right now there are a number of options—each with its own set of challenges—and that’s what’s holding things up. It’s clear that Intel will march on to the next process nodes—my sources say the path is clear for Intel all the way down to 7nm using bulk CMOS and quadruple or even quintuple patterning coupled with limited use of EUV. IBM likewise will push the boundaries of high performance and low power in all directions, at advanced nodes using some exotic techniques that will likely be bound more by reliability than cost.

But for the rest of the market—the fabless companies that have to compete for sockets as well as the captive internal makers of chips that have to compete on overall price—all options are on the table. This is system-level finance at its most complex, and teams are now assessing the costs, the risks and the available and future options that could provide an edge against potential competition.

When things really start moving forward again—or sideways—is anyone’s guess. But the pressure is certainly building for something to happen.