Architecting chips for maximum performance, low power, and configurability.
More intelligence is now required in the front-, mid-, and back-haul for 5G/6G communication, requiring a mix of high performance, low power, and enough flexibility to accommodate constantly changing protocols and algorithms. One solution to these conflicting goals involves reconfigurable DSPs, in which the processing element is hardwired like an ASIC but still configurable for a variety of applications and implementations through software. Jeremy Roberson, technical director and software architect for AI/ML at Flex Logix, talks about partitioning DSP architectures for maximum performance per watt, while maintaining enough flexibility for future-proofing designs.
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