Thermal issues present ongoing reliability issues.
As previous articles in this series have discussed, advanced packages introduce new materials and new reliability concerns. Diffusion into solder bumps can create brittle, high resistance, intermetallic compounds. Heat transfer through an interposer can degrade the lifetime of even cool, low power chips. Still, through-silicon vias are unique in that they cut directly through the integrated circuit itself.
While copper is no longer new to integrated circuit manufacturing, the clean vertical edges of interconnect metal layers are quite different from the rough, scalloped edge left by TSV etching with the Bosch process. TSV etching sacrifices sidewall quality for speed, leaving a rough profile that makes conformal SiO2 liner and PVD barrier layer deposition much more difficult.
Making matters worse, according to SMIC researcher Yong Lv, the coefficient of thermal expansion of silicon is only 2.6 ppm/ºC, compared with 17.5 ppm/ºC for copper. Annealing during the manufacturing process can lead to “protrusion” defects, where the compression imposed by the relatively rigid silicon extrudes copper out of the via cavity. Repeated thermal cycling over the life of the part can crack the barrier and liner interfaces at the top and bottom of the via, allowing copper diffusion into either the adjacent interconnects or the silicon. Electromigration can exacerbate this effect: as in solder bumps, current follows the path of least resistance. The resulting current crowding increases current density at the via-interconnect connection points.
Process optimization can help minimize these effects. Bharat Bhushan and colleagues at Applied Materials found no evidence of interface delimitation or cracking after 1000 thermal cycles with their “via middle” TSV process.
A few researchers have also proposed the use of open TSVs to reduce the effects of CTE mismatch. After barrier and seed layer deposition, most TSV designs use electrochemical deposition to create a solid copper cylinder. Open TSVs form a hollow tube instead, with current flowing along the metallic walls. In simulations using an open aluminum cylinder with a tungsten liner, the highest stress and vacancy concentrations occurred along the aluminum/tungsten interface. It is still unclear whether open TSVs will offer a useful alternative, though.
In some ways, TSVs are the simplest component of an advanced package design. Copper, silicon, and barrier materials are well known to the industry. Still, particularly as via density and current density increase, designers must be alert to the potential for cracking at the complex interface between wafer and via.
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Why not use tungsten instead of copper? The CTE match is much better.
When it comes to transistor nodes SMIC has been a perennial late comer, still several generations behind the leading logic Foundries. The same holds for TSVs as there are now memory products out there using TSVs in the middle of the die. Hence quoting only a SMIC “Researcher” in a review article on TSVs is misleading. Cu “pumping” out of TSVs due to CTE mismatch has been solved. But the CTE mismatch derived issue that is still outstanding is shifts in transistor characteristics due to mismatch stresses from adjacent TSVs. This requires Keep Out Zones which affects placement & routing and is one of the headaches hindering the use of TSVs in Logic dice like SoCs that have diverse functional blocks ea. requiring their own cluster of TSVs so as to keep the planar interconnects short.
While I agree with the basis of your discussion of CTE mismatch between Cu and Si in TSVs, abandoning or even redesigning TSVs is not the best solution. We believe the answer is to reduce the TSV diameter to reduce stress. aveni processes enable this solution. We have addressed this in a recent blog post: “Solving the CTE Mismatch in TSVs.” https://www.linkedin.com/pulse/solving-cte-mismatch-tsvs-frederic-raynal