Unlocking The Value Of Yield

Have you stopped to consider the impact of yield on your overall product cost? Of course you did, when you considered your yield targets and set your product goals. But is it good enough to stop once the goals are achieved, or should you find ways to drive additional value into your organization once production has begun? What is the value of a 1% improvement in product yield? The short answer is that it can amount to millions of dollars per week for a high-volume device if you can identify systematic or manufacturing defects. This type of savings can be realized using yield tools like diagnosis-driven yield analysis (DDYA).

Where yield learning can happen

Products undergo several stages of manufacturing and test as they transition from raw materials to finished goods. In the case of semiconductors, these stages include Wafer Testing, Package Testing, System-Level Testing and, finally, a System Test of the completed product. With proper system architecture and data collection strategies, yield learning can occur at any stage (figure 1).

Fig. 1: Yield learning can occur at every stage of manufacturing and test.

There is a trade-off between the cost of test time and scrap material throughout the manufacturing and test stages. Wafer testing aims to identify the highest percentage of failures in the shortest time. This is why structural testing and Automatic Test Pattern Generation (ATPG) have become essential in our industry. To achieve a profitable product, it is important to identify more than 90% of the failing parts at this stage.

Detecting all defects during wafer testing can sometimes be challenging. Some defects can be elusive and harder to identify, and some are activated by specific patterns. Regardless of where defects occur, the number of patterns needed to capture the remaining percentage of failures can exceed the cost-efficiency goals for testing.

Collecting sufficient failure data is essential to maximize learning. By collecting data on all failing parts from characterization through production, we can greatly improve the impact of our yield learning efforts (see figure 2).

Fig. 2: An example of potential yield improvement in the wafer testing phase.

The generation and application of tests should be designed to ensure the fewest number of test escapes by ensuring adequate fault coverage across the wafer test stage to the package testing stage. The objective is to maximize the number of functional parts to achieve the highest possible yield.

Fig. 3: An example of cost savings based on yield loss. Even a slight improvement in yield can lead to significant cost savings.

Each of these stages introduces increased costs related to scrap and effort. If the device under test is deemed defective, it negatively impacts profitability. Therefore, the effectiveness of each test must be carefully evaluated. In some situations, a test may be advanced to an earlier stage if the failure rate rises (shifted left), while in other cases, it may be delayed to a later stage when the failure rate is lower (shifted right).

The role of diagnosis in yield analysis

Scan patterns created by an ATPG tool are the standard for testing digital designs in manufacturing. These scan patterns include both the stimuli and the expected good responses, which are determined by simulating the logical design. During manufacturing, the design is tested by applying ATPG-generated scan patterns using automated test equipment (ATE), which captures any failing responses.

Scan diagnosis has historically been used to locate defects. When defective devices are identified as indicative of a yield issue, diagnosis is employed to determine the most probable locations of these defects. Volume scan diagnosis results provide insights into design layout and failure data rather than depending only on manufacturing process data. Streamlining the identification process allows for quicker resolutions to yield issues.

Diagnosis-driven yield analysis (DDYA) uses diagnosis to locate defects and identify the underlying root causes. This technology leverages production test results, volume scan diagnosis and statistical analysis to identify the causes of yield loss in IC chips. DDYA helps select the most suitable candidates for physical failure analysis (PFA) within a batch, such as a wafer or many failing devices. This approach aids in ramping up yield for new manufacturing processes and products, improving yield for established processes and enabling compliance with test quality standards.

Machine learning to find trends in scan fail data

Rules-based systems were first employed about 15 years ago to improve scan diagnosis. Probability-based diagnosis grouped faults based on known/expert characteristics, filtering many candidates into the most likely suspects. This resulted in more than 5x fewer suspects in a diagnosis call-out.

This type of machine learning, a type of artificial intelligence (AI), can help identify trends that may be difficult for humans to recognize. For yield learning, AI’s strength is in combining data, building up higher-level relationships and uncovering additional yield limiters. (Read more about using AI for advances in test and yield learning in this solution brief.)

DDYA leverages industry-leading machine learning to uncover previously unknown systematic issues, providing up to 85% shorter PFA (Physical Failure Analysis) cycle time. Seven of the top ten semiconductor manufacturers have adopted DDYA technology for yield improvement.

Fig. 4: The application of machine learning to improve yield.

Diagnosis-driven yield analysis in practice

The Siemens EDA Tessent Diagnosis solution handles all major defect mechanisms. Its advanced scan chain diagnosis capability handles composite defects that affect chain and functional operation. Tessent Diagnosis turns failing test cycles into valuable data by correlating design information and failure data from manufacturing test with scan patterns from Tessent FastScan or TestKompress. It determines a defect’s most probable failure mechanism, logic location and physical location using cell-aware and layout-aware technology. This detailed analysis of devices that fail manufacturing test greatly reduces the failure analysis effort and creates the foundation for diagnosis-driven yield analysis.

With the advent of newer process technologies, particularly those featuring finFET transistor designs, defects at the transistor level in the front-end-of-line (FEOL) stages have become the main challenge affecting systematic yields for modern semiconductor manufacturers. Tessent products, such as Tessent Diagnosis, incorporate the latest technologies to stay in front of these types of challenges.

Tessent Hi-Res Chain Diagnosis, an option to Tessent Diagnosis, provides accurate transistor-level isolation for scan-chain defects. On advanced process nodes like 5nm and below, where the yield ramp relies on chain diagnosis, this capability can improve the diagnosis resolution by >1.5X. This resolution savings can lead to FA avoidance, saving the semiconductor design company millions of dollars per product.

In conclusion

In traditional failure analysis, the primary goal of diagnosis is to identify the specific defect causing failures in a particular chip. However, for yield analysis, merely locating the defect isn’t sufficient. If all the failing chips on a wafer show defects in various locations or circuits, many of these failures may still stem from the exact underlying defect mechanism or root cause.

Yield learning is effective at all stages of the yield ramp cycle, from wafer to package and system-level tests. Applying yield analysis based on volume scan diagnosis results rather than relying on manufacturing process data alone can reduce the cycle time to the root cause of yield loss by 75 to 90 percent.

Tessent Diagnosis can provide diagnosis-specific ATPG algorithms to accelerate the FA process. Based on initial diagnosis results, additional patterns can be generated to improve diagnosis resolution further. Tessent Diagnosis provides the highest accuracy rate and is validated at multiple advanced technology nodes from 130nm to 3nm. On average, more than 80% of reports generated using Tessent Diagnosis have been confirmed using an FA process. Tessent Diagnosis results have also been used to ramp yield across multiple nodes.

For a more detailed discussion, see the whitepaper Chain Diagnosis Improvements for the Age of Backside Power or listen to a recent webinar on Chain Diagnosis.