Use Cases And Value Proposition Of eFPGA

Flex Logix EFLX eFPGA is the first eFPGA that enables a customer to match the performance of FPGAs from AMD/Xilinx and Intel (in the same process node) with the same density (LUTs/mm2). EFLX eFPGA has been in use with customers now for more than 5 years, hardware and software.

More than 40 chips have been licensed to use EFLX eFPGA and more than 20 chips are working in silicon. Big customers like Renesas are planning high volumes and families of chips using eFPGA.

Many customers are evaluating eFPGA and a common question is, “what are the use cases and reasons for using eFPGA by existing customers?” There are numerous reasons as discussed below.

Cost and power reduction

Many volume applications use FPGA because they need in-field reconfigurability (changing standards, changing algorithms, etc) but they want to improve their system’s competitiveness (power, size, cost). FPGAs are bulky, expensive and power hungry. Integrating eFPGA can greatly improve the economics while maintaining full reconfigurability and performance.

An FPGA’s cost is 65% the margin made by the manufacturer – all of that goes away with integration.

About 1/3 of an FPGA’s die area is the analog PHYs for the high-speed interfaces. Most of these go away with integration.

We’ve found with customers that a significant portion of the LUTs in their designs don’t change with reconfigurations: they are fixed buses to bring data to and from the reconfigurable core.

This can be hardwired so the number of LUTs needed in the SoC is typically half of what’s in the FPGA.

There is also a lot of cost of voltage regulators for an FPGA that disappear with integration.

Typically, the cost of eFPGA is 1/10^th the cost of the FPGA it replaces but with the same speed and programmability.

Power can also be cut to 1/10^th because most of the power in an FPGA is the power-hungry PHYs that are mostly not needed when using eFPGA in the SoC.

Performance increase

FPGAs commonly operate as co-processors to accelerate certain functions (DSP, encryption/decryption, etc.) working in conjunction with host processors. Communication is done over PCIe.

PCIe can be high bandwidth but also has high latency. For an FPGA and host processor to communicate, the latency is the AXI bus latency on the host to the PCIe, the latency through the host’s PCIe (serializer), the length of the packet transferred (header plus data – short packets result in less latency but less effective bandwidth too), and the latency through the FPGA’s PCIe (de-serializer).

If instead there is eFPGA on the host processor’s AXI bus, the latency between the processor and eFPGA is only the AXI bus latency – much less than going through PCIe. For many applications this can significantly boost system performance.

Flexibility for customer value-add increases TAM

Many of our customers using eFPGA are not integrating an existing FPGA.

Instead, they are seeking to increase the flexibility and adaptability of their chip to address customer demands:

• Configurable GPIO: there are many flavors of UARTs, SPIs, etc. Only a few versions are hardwired in an SoC. In the past, for a large customer, a manufacturer might do a metal mask version to implement a special UART. At finFET node mask costs, that is not practical. Now a lot of customers use small FPGAs to handle “translation” between the flavors of GPIO-based protocols. By integrating 4K-8K LUTs of eFPGA on the peripheral bus (see block diagram above) any type of GPIO protocol can be handled.
• Configurable acceleration: there are many types of encryption/decryption or compression/decompression and other algorithms. Only so many can be hardwired. With eFPGA on the AXI bus a customer can program any algorithm they want and with FPGA parallelism it will process data faster than the processor itself can.
• Secret sauce: many large OEMs don’t want to disclose their special algorithms to the SoC maker. They now implement them in an FPGA, but to cut power/cost they can achieve the same result with an eFPGA on the AXI bus (and cut latency which can boost throughput).

The cost for bringing an advanced finFET node SoC to market is $50 million and climbing. To justify this development cost, the market TAM needs to be in the $100s of millions. Having a chip that is adaptable can increase the range of customers and applications that can use it.

USA manufacturing

Our US defense customers (DoD, DoE, other agencies, and their prime contractors like Boeing) use FPGAs extensively in most defense systems. But most FPGAs are manufactured in Taiwan which is claimed by China – this presents a serious supply risk.

We have ported EFLX eFPGA for Sandia in their 180nm proprietary fab in Albuquerque. We have ported EFLX eFPGA for GlobalFoundries 12LP/LP+, which is fabricated in upstate NY. We have begun design of EFLX eFPGA for TSMC N5 and N3, which will be manufactured in Arizona as well as in Taiwan.

Other ports of EFLX eFPGA to US fabs are in evaluation by various US government entities. We have also ported eFPGA for RadHard by Design using our customers’ RadHard cells.

Summary

eFPGA enables numerous applications to reduce cost, reduce size, increase performance, increase TAM and reduce supply risk. For these reasons, the adoption of eFPGA is just beginning and is accelerating.