A method for adding testability and visibility into advanced HBM3 interconnects.
Since its introduction in 2014, High Bandwidth Memory (HBM) has been poised to address the growing demand for high-performance, high capacity, and low latency memories required by High-Performance Computing (HPC), high-performance graphic processors (GPU), and artificial intelligence (AI). Since then, bandwidth and capacity requirements have increased with each new generation: HBM2, HBM2e and now HBM3.
Global Unichip Corporation (GUC) is at the forefront of the development of HBM3 Physical Layer (PHY) Intellectual Property (IP) with its latest silicon-proven product, supporting up to 8.4 GT/s on 5nm process node and featuring up to 8.8GT/s on 3nm.
With these advanced technologies comes a plethora of challenges. Dies are assembled over the silicon interposer using very small micro-bumps, which may suffer from latent defects such as voids or cracks, potentially posing a reliability risk to the assembled product. Although rare, these latent defects could cause a system failure over time if not screened out during the final test or detected during in-field operation. At the same time, standard Automated Test Equipment (ATE) cannot test those links since they are not exposed on the primary interfaces, essentially becoming “blind spots”.
This white paper discusses a method for adding testability and visibility into advanced HBM3 interconnects.
By downloading this white paper, you’ll discover:
Click here to read more.
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