System-Level Design
WHITEPAPERS

Using PCIe Real World Interface For High-Speed Hybrid Prototyping

An approach to hybrid prototyping using a PCIe interface between the HAPS FPGA-based prototyping and the Virtualizer virtual prototyping.

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This white paper highlights a novel approach to hybrid prototyping using a PCIe interface between the HAPS FPGA-based prototyping and the Virtualizer virtual prototyping. The use of PCIe real world interface helps to deliver a prototyping system, running fast enough to enable embedded software development and hardware-software co-validation in the shortest possible time. The hybrid prototyping example consists of a Virtualizer Development Kit (VDK) comprised of an Arm Cortex-A53 CPU model, Synopsys DesignWare PCIe root complex model, PCIe end point proxy model and DRAM model and a HAPS-80 FPGA-based prototyping setup comprised of PCIe end point controller and block RAM controller RTL. Xilinx PCIe endpoint IP has built-in DMA subsystem enabling DMA transfers between block RAM memory RTL on HAPS-80 FPGA system and DRAM fast memory model inside the VDK. Xilinx DMA subsystem for PCIe IP has been also customized to enable DMA bypass interface. In order to physically communicate the virtual prototype model transactions from workstation to HAPS hardware system, Synopsys PCIE4_MGB kit along-with RISER1_MGB card and PCIE-x4-x8_CABLE is used as high-speed and low-latency physical communication link. Xilinx PCIe DMA driver code is ported on the VDK Linux machine executing over Arm Cortex-A53 CPU Fast Model.

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