Using Virtual Metal Fill To Predict The Impact Of High Level Nets

A recent blog post discussed the use of virtual metal fill (VMF) to predict the effects of real metal fill when performing RC extraction on a chip layout. This enables static timing analysis (STA) closely correlated with final post-fill results without incurring the time to perform the actual metal fill insertion during the layout-STA loop. VMF is fast enough to be run in every iteration of this loop, so it has no negative effect on the project schedule or time to market (TTM).

The VMF flow described in the previous post is very effective at predicting the effects of metal fill within a block of the chip design. Of course, all the blocks must eventually be interconnected by signals at the top levels of the chip hierarchy. To avoid disturbing a hardened block or macro that has already been placed and routed, especially when it is instantiated multiple times, the high level nets use additional metal layers above the layers within the block.

These interconnections are sometimes called over the hierarchy (OTH) nets, and they affect intra-block timing due to capacitive coupling with lower level signals. In addition, the higher layers also require metal fill to ensure uniform density so that Chemical Mechanical Polishing (CMP) can planarize the wafer. These metal fill polygons also create capacitive coupling with the functional logic within the block, and therefore also affect STA results.

Full chip design with over the hierarchy (OTH) nets on block level cells.

Fortunately, the concept of virtual metal fill at the block level can be extended to predict the effects of the OTH nets before the full chip is placed and routed or real metal fill is performed. VMF is easier to use and provides more accurate results than the traditional metal sheet over area (MSOA) approach, in which a single grounded rectangle covering the block is used to model capacitive coupling.

MSOA is largely a manual effort, in which the designer must define the higher metal layers and the metal sheet before performing RC extraction. This requires accessing the design database to determine the dimensions needed to cover the block being analyzed. Just as it is within the block, VMF for OTH nets is an automated process that happens during extraction with minimal setup needed by the designer.

Another issue for MSOA is that it can create shorts between the metal sheet and nets in the design. This violates design rules, so a clean design rule check (DRC) run on the model is not possible. VMF follows the same design rules for OTH nets as it does within the block, so the resulting model is DRC-compliant in terms of rules for separation, metal density, and orientations.

Block level design with over the hierarchy (OTH) fill polygons.

In addition to being easier to use, VMF for OTH nets provides more accurate extraction and timing results than MSOA. It uses a model that considers track fill on the higher metal layers rather than a simple sheet model. This more realistic model leads directly to a better correlation between STA runs at the block level and signoff STA after full-chip place-and-route and real metal fill on all layers.

Predicted capacitance for OTH nets using MSOA tends to be optimistic when compared to final values. This can lead to unpleasant surprises during STA runs, with some paths not meeting their expected timing. When this happens, signoff is impossible until these paths are fixed, costing valuable project resources and delaying TTM.

In contrast, OTH net capacitance using VMF models is accurate within 3% of actual values from the hierarchical design context. This means that final extraction and STA results will be closely correlated to the VMF runs, so signoff can occur quickly and predictably. If required, VMF characteristics can be set up for individual layers to increase the accuracy of the model even further. While it is easy to run VMF with default values, users have fine grain control available when desired.

Additionally, block level timing engineers would like to identify coupling capacitance contributions from nearby and hierarchical critical signal nets in a more detailed fashion to understand the timing impact on the lower level block before the top level design is available. The traditional way of modelling this scenario involves manual modifications to the design.

Leveraging the VMF with OTH methodology, the block level engineers can define driver and load cell type of the virtual net (virtual attacker/aggressor) to extract the cross-coupling capacitance to the block level nets. Virtual nets can be clearly differentiated from the VMF in the parasitic netlists to allow downstream STA tools to identify coupling contributions from virtual attackers. The impact of the virtual aggressor is easily recognized by a more pessimistic negative slack from the timing reports.

STA report comparing the increase in pessimistic negative slack due to VMF attacker nets.

The Synopsys StarRC parasitic extraction solution combined with Synopsys PrimeTime static timing analysis solution provides VMF implementation for OTH nets as well as for nets within the block. PrimeTime STA solution accurately models the cross coupling for both setup and hold checks allowing block level cells to signoff with higher accuracy before integrating with top level design. It is simple to set up and use, requiring neither manual metal sheet definitions nor error prone user created FILL parameter files.

Synopsys StarRC supports metal fill done by the designer or by the foundry. It is equally applicable to pure digital flows, custom/analog flows, and mixed-signal designs. This VMF solution can be used with any design implementation platform, including third-party place and route tools, and it supports the industry-standard STA solution. It meets the requirements for both speed and accuracy to address the limitations of the traditional flows.

Modeling the cross-capacitance impact from high-frequency, high level routing on individual blocks is essential, especially in designs with multiply instantiated macros. Chip designers can adopt Synopsys StarRC VMF today, solving the very real problems of complex flows and TTM delays. The designers can be confident in a fast, accurate solution that will get even better over time.