Using Virtual Metal Fill To Solve Real Design Problems

Predicting metal fill effects while performing RC extraction.


People learning about semiconductor manufacturing might well be confused by the concept of metal fill. It seems perfectly intuitive that laying out a complex chip will result in some regions with fewer transistors and metal interconnect than others. It makes sense that there will be areas that are mostly empty. So why spend money on more complicated masks and on extra metal just to fill those empty spaces?

The answer is that metal fill aids the chip fabrication process much more than it complicates it. Uneven deposition of metal on a layer results in non-planarity. Variations in thickness make it more difficult for Chemical Mechanical Polishing (CMP) to planarize the wafer before additional layers are deposited. Metal fill creates uniform density before CMP by adding polygons to the empty spaces between functional elements on the wafer, and it is often used on all layers.

Metal fill is different from interconnecting traces because the shapes are chosen for geometric rather than for functional reasons. However, the added metal interacts with the chip design, affecting the design resistance and capacitances. There is capacitive coupling between the metal fill polygons and the functional logic, which influences chip timing, so it must be taken into account at some point during the development process. Designers have had two traditional ways to handle this requirement.

The simpler approach is to ignore metal fill until signoff. The design is placed and routed, RC values are extracted, and static timing analysis (STA) is performed without performing or considering metal fill. This loop is executed many times as the design evolves, bugs are fixed, and timing is closed. When the design is believed to be ready for signoff, metal fill is inserted, and RC extraction is rerun to take the capacitive coupling into effect.

Since adding a large number of metal polygons changes timing results, the would-be “final” STA run is certain to report violations. These must be resolved before signoff is complete, but fixing the violations may require numerous engineering change order (ECO) loops, each including RC extraction and STA. Since these iterations occur very late in the design process, they can delay the project schedule and the all-important time to market (TTM).

The second traditional approach is performing the insertion after each place and route step during the layout phase. This enables extraction and STA to account for the effects of metal fill on every iteration and produces accurate timing results. The problem with this method is that inserting metal fill adds significant time to the layout loop. Inserting metal on every layer may add hours to every iteration, slowing down the development process and lengthening TTM.

Neither of the traditional flows is sufficient for today’s large and complex chips. Designers need a solution that does not delay the schedule but that delivers a high correlation to “real” metal fill in terms of extraction and timing accuracy. Key metrics such as worst negative slack (WNS), total negative slack (TNS), and number of violating paths (NVP) must change minimally after adding metal fill. The solution must also be easy to use and able to leverage existing data.

Virtual metal fill (VMF) delivers just such a solution. This method provides a highly accurate prediction of metal fill effects in the process of performing the RC extraction. Thus, the ensuing STA is also highly accurate. The timing results correlate closely with STA after the real metal fill, which needs to be performed only once during signoff. VMF is fast enough to be run in every iteration of the layout loop, so it has no negative effect on the project schedule or TTM.

The Synopsys StarRC parasitic extraction solution provides VMF implementation. Unlike traditional methodologies that rely on error prone user created FILL parameter files, StarRC can take the data from any existing design with metal fill and generate a parameter file, fully compliant with the foundry rules, for the VMF runs. This results in much faster runtimes, improving the turnaround time (TAT) for each layout iteration. Alternatively, StarRC can also use foundry provided metal fill rule decks to generate VMF parameter file.

This solution supports metal fill done by the designer or by the foundry. It is equally applicable to pure digital flows, custom/analog flows, and mixed-signal designs. This VMF solution can be used with any design implementation platform, including third-party place and route tools, and it supports the industry-standard STA solution. It meets the requirements for both speed and accuracy to address the limitations of the traditional flows.

The following table summarizes some of the key metrics as measured on an actual chip design. VMF runs 3X faster than real metal fill, so it can be used in every iteration. The RC extraction results are within 1% of those for metal fill. For timing, WNS, TNS, and NVP are also all very close to the final signoff values, just over 1% difference in the worst case. This ensures that there are no unpleasant surprises late in the schedule.

Traditional flow is Real Metal Fill insertion + StarRC extraction. VMF flow is Virtual Metal Fill insertion + StarRC extraction.

VMF is an area of active development, with ongoing efforts to expand beyond individual blocks to consider metal fill effects across elements in the design hierarchy. Future blog posts will discuss some of this work. Chip designers can adopt Synopsys StarRC VMF today, solving the very real problems of complex flows and TTM delays. The designers can be confident in a fast, accurate solution that will get even better over time.

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