Virtual Packages Improve Signal Integrity

How to optimize chiplet architectures, including reducing in-package loss and trace length.


The 112 Gb/s generation of SerDes has brought along excessive loss within the package, around 5 dBs of loss within each monolithic package. This loss markedly reduces the usefulness of these SerDes.

MCM technology has progressed to where the use of 70mm packages is routine. Non-interposer MCMs easily can use 20 or more chiplets, plus large dies and passives can be used. These MCMs have low yield loss because their pad pitch is much larger than MCMs that use interposers.

Several chiplet architectures are possible. One good approach puts the entire Ethernet I/O subsystem in the chiplet, including the RS, MAC, PCS and FEC layers, as well as the PHY layer with its long-reach SerDes. Removing these blocks from the switch chip raises its yield. Spreading the functionality into chiplets also has the effect of distributing the heat around the MCM and away from the central switch chip. Chiplets also allow the best semiconductor process to be used for each die, and they can allow multi-vendor ecosystems to thrive.

These chiplets are then placed around the perimeter of an MCM. Done carefully, an MCM layout can create smaller virtual packages around each of the chiplets. These virtual packages have sharply reduced trace length and thus much reduced in-package loss. Two dBs or more of loss can be saved in each package, which is a significant improvement.

If the Ethernet I/O subsystem is placed in the chiplet, then the protocol between switch-chip and the chiplet is not a PMA-style serial type. Instead, it is a fat-pipe packet-style interface that runs with credit-based flow control and employs a speed-up factor. With this type of interface, an optimized femto-SerDes can be used.

A second style of chiplet is also possible that extends 8 PMA interfaces to each chiplet, including only a thin layer plus eight (or Nx8) SerDes blocks in each chiplet. This solution can support full clock transparency using digital PLLs.

A package study was conducted by Kandou to characterize the trace length reduction available with chiplets and virtual packages. A 70mm BGA package was analyzed for three cases—no chiplets, 4 chiplets and 16 chiplets. The trace length of the longest switch-bump to chiplet-bump trace and the longest chiplet-bump to package-ball trace for each case was identified.

Fig. 1: Characterizing the trace length.

In the monolithic case, the longest trace runs from the switch-chip to the corner package ball with insertion loss as high as 5dB, a substantial percentage of the total loss budget for a long-reach SerDes.

Fig. 2: Kandou’s Glasswing USR SerDes utilizes a new modulation technique called CNRZ-5, which offers low power (1 pJ/bit), better error performance as compared to PAM-4, with enough reach to allow the chiplets to be placed in the corners of a large MCM.

By building a chiplet using the SerDes as the interface to the SoC, and placing the LR SerDes on the opposite edge of the chiplet, chiplets can be positioned closer to the package balls. In an example using 16 chiplets, the longest SoC-to-chiplet trace runs to the corner chiplet and the longest chiplet-to-package ball trace runs from the corner chiplet to the corner package ball. A virtual package, shown in green, surrounds each of the sixteen chiplets and demarcates the package ball serviced by each chiplet.

Leave a Reply

(Note: This name will be displayed publicly)