Why a flow is essential to identify differences in design schematics and layout views for an analog/mixed-signal SoC.
A document, whether it is stored as a simple text file or as a word processor formatted file, is often a living entity that is constantly evolving. A user may create a first draft, revise it multiple times, have other team members review it and make alterations, and refine it over time to keep up with new information and requirements. What has changed since the last revision becomes very important to know, otherwise you would spend a lot of time reviewing the same document in its entirety multiple times. Not only is this highly inefficient, it is highly frustrating and impossible to know if you even reviewed all the changes made since the last review.
The same problem exists in the semiconductor design domain, where design teams are spread across multiple sites with a number of designers constantly editing various versions of the same design files, textual and binary alike. Here, identifying the differences becomes a very complex, yet necessary, problem to solve. Identifying the differences in a design — either a VHDL or Verilog file, a schematic or a layout — becomes critical in the face of tight design schedules and distributed design teams. An edit made by one designer at a design site can impact the work of another designer from the same team at another location. In such a case, identifying the differences to narrow down a problem becomes critical.
While a skeptic may argue that the original Unix diff command is sufficient for checking and verifying design changes, the reality is that the concept of identifying differences needs to be extended to an entire design hierarchy. Not only that, but a design can also include schematic for an analog design, which cannot be parsed by the Unix diff command. Presenting the key differences in a meaningful format while removing the “noise” is equally important.
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