Wafer Bin Map Defect Classification Using Semi-Supervised Learning

A new technical paper titled “Semi-Supervised Learning with Wafer-Specific Augmentations for Wafer Defect Classification” was published by researchers at Korea University.

Abstract

“Semi-supervised learning (SSL) models, which leverage both labeled and unlabeled datasets, have been increasingly applied to classify wafer bin map patterns in semiconductor manufacturing. These models typically outperform supervised learning models in scenarios where labeled data are scarce. However, the challenges posed by wafer bin map data in applying conventional image augmentation methods, particularly within SSL frameworks such as FixMatch, have not yet been fully addressed despite their significant role. Recognizing the importance of thoughtful implementation of weak and strong augmentations within FixMatch, we propose a method that incorporates saliency map information into cutout augmentation. This approach preserves essential regions crucial for wafer defect pattern classification and thus improving model performance. Our approach achieves a macro F1-score of 0.841 with only 5% labeled data, surpassing state-of-the-art methods by 6.2% compared to WaPIRL and 7.5% compared to Manivannan’s method. Similarly, with 10%, 25%, and 50% labeled data, our method achieves F1-scores of 0.856, 0.874, and 0.891, respectively, showing improvements of 3.5%, 1.7%, and 1.2% over WaPIRL and 5.0%, 6.6%, and 11.9% over Manivannan’s method in each case. Experimental results indicate significant improvements in defect pattern classification by avoiding cutting important regions in cutout augmentation. The proposed method achieves new state-of-the-art performance in wafer bin map defect classification, demonstrating the potential of our tailored augmentation techniques and the effectiveness of incorporating saliency map information reflecting the characteristics of wafer bin maps.”

Find the technical paper here.  December 2024.

U. Jo and S. B. Kim, “Semi-Supervised Learning with Wafer-Specific Augmentations for Wafer Defect Classification,” in IEEE Access, doi: 10.1109/ACCESS.2024.3522180.