Week In Review: Design, Low Power

Intel buys NetSpeed; embedded vision design kit; photonics layout.


Intel acquired NetSpeed Systems, a network-on-a-chip and interconnect fabric IP and tool provider. Founded in 2011, the San Jose-based company recently put a focus on interconnects designed with AI applications in mind. Intel has cast the acquisition as a way to tie a number of its other technologies together. The team will join Intel’s Silicon Engineering Group. Intel has been a NetSpeed customer, and Intel Capital participated in multiple funding rounds. Intel stated that it will honor NetSpeed’s existing contracts, while transitioning the team to an internal asset in the future. Terms of the deal were not disclosed.

Renesas will acquire analog mixed-signal provider Integrated Device Technology. Founded in 1980, IDT’s primary product lines include RF, high performance timing, memory interface, real-time interconnect, optical interconnect, wireless power, and sensors. Renesas, a big name in automotive, will pay about $6.7 billion in cash for IDT. The deal is expected to close in the first half of 2019.

Tools & IP
Synopsys uncorked the High-Performance Core (HPC) Design Kit for EV6x Embedded Vision Processors. New specialized standard cells focus on improving the power efficiency of MAC operations. The kit contains fast cache memory instances, ultra-high-density two-port SRAMs, and a suite of cells including multi-bit flip-flops, compressors, and multiplexers for optimization of the processor’s vector DSPs and CNN engines. Options for overdrive/low-voltage process, voltage, and temperature (PVT) corners, multi-channel cells, and memory built-in self-test (BIST) and repair are also available.

Mentor launched an integrated photonic automated layout system, LightSuite. Users can describe designs in Python, from which the tool automatically interconnects photonics components with curved waveguides to produce designs ready for fabrication. It will also route electrical connections simultaneously along with the waveguides.

Synopsys updated its CODE V optical design software, adding specification tracking tools, mechanical constraints for optimization and manufacturability, multilayer coating prescriptions, generation of machine-readable files for aspheric surfaces, as well as an expanded library of pre-built specifications.

Arasan Chip Systems debuted a lower area MIPI C-PHY / D-PHY Combo IP Core compliant to both the C-PHY and D-PHY Version 1.2 specifications. It can support the latest D-PHY 2.1 specification upon request. The IP targets users who may need a D-PHY only design currently, but may need to support C-PHY in the future.

eSilicon validated its 7nm 56G long-reach SerDes in silicon, saying the design is meeting or exceeding the target performance, power and functionality. Features include high insertion loss tolerance with low bit error rates, support for Ethernet, OIF, Interlaken and Fibre Channel standards, and a flexible clocking architecture.

Allegro DVT announced its AL-E120 encoder IP with support for HEVC scalable extension (SHVC).  The IP targets high-end video applications and supports H.264/AVC, H.265/HEVC, VP9 video formats and JPEG still images at resolutions up to 8K, while improving video quality by up to 20% compared to the company’s previous products. Allegro DVT also released compliance streams and test suite for the AOMedia Video Codec 1.0 (AV1) specification.

Truphone’s embedded SIM (eUICC) software has been added to Synopsys’ DesignWare tRoot Hardware Secure Module (HSM) for integrated SIM (iSIM) to enable secure, over-the-air remote provisioning and operating system updates for cellular IoT devices.

Electronic Design Process Symposium (EDPS): Sept. 13-14 at SEMI in Milpitas, CA. The meeting will discuss design methodologies, design flows and CAD tool needs. Focus areas include machine learning, smart manufacturing, reliability, and cybersecurity.

AI Hardware Summit: Sept. 18-19 in Mountain View, CA. Focused on the development of hardware accelerators for neural networks and computer vision, the conference features talks from AI chip startups to well-established companies.

Digital Marketing Workshop 2.0: Oct. 3, 6 p.m. – 8:30 p.m. in Milpitas, CA. A workshop focused on three organizational shifts that are key to mastering digitally-driven marketing and sales and conducting marketing in an agile manner.

Arm TechCon: Oct. 16-18 in San Jose, CA. The Arm-centric conference and expo will feature keynotes by senior Arm executives as well as best-practices for implementing Arm IP in a range of designs, including IoT and automotive. The company has also teased an expanded roadmap for future products to be released at the show.

RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.

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