Week In Review: Design, Low Power

Siemens will acquire UltraSoC, a provider of embedded analytics and monitoring solutions for applications including cybersecurity and functional safety. Founded in 2006 and based in Cambridge, U.K., the company’s technology will be integrated into the Xcelerator portfolio as part of Mentor’s Tessent software product suite where it will form part of a ‘Design for Lifecycle Management’ strategy. Terms of the deal were not disclosed; it is expected to close in the fourth quarter of 2020.

Tools & IP
Imagation Technologies inked a deal with Rockchip, which will use Imagination’s RF and baseband low-power Wi-Fi IP in its next chip. Behind the scenes, low-power Wi-Fi is in a race against other LP technologies, such as Bluetooth Low Energy, for the fastest communication using the least amount of energy in battery-powered devices.

Aldec added VHDL-2019 feature support and a UVM Registers window to the Riviera-PRO high performance simulation and debugging tool. The VHDL-2019 features supported are: Interfaces; Conditional Compilation; Shared Variables on Entity Interfaces; API for Assert (without PSL); API for Calling Path Information (in debug mode); Conditional Expression; and API to access Date, Time and File System.

IAR Systems added support for trace as implemented by SiFive Insight to its IAR Embedded Workbench for RISC-V development toolchain. The Workbench supports RV32 and RV32E 32-bit RISC-V cores and ISA extensions including C, F, and D.

Lattice Semiconductor launched the Certus-NX family of FPGAs. The company says the general-purpose FPGAs provide high I/O density and power savings compared to others in its class and support instant-on performance and fast PCIe and Gigabit Ethernet interfaces. It is based on 28nm FD-SOI process technology.

Rianta Solutions released 200G/400G Single Channel Ethernet MAC/PCS/FEC IP. The Ethernet core is available with a UVM verification environment for integration and full chip validation testing as well as a complete software API/SDK.

Deals & Awards
Synopsys was selected as a participant in DARPA’s Automatic Implementation of Secure Silicon (AISS) program. The program’s goal is to automate the inclusion of scalable hardware security mechanisms in IP and SoCs to explore security versus other design trade-offs. Synopsys will supply DesignWare Security IP and will develop critical design-to-manufacturing flows. As part of the four-year AISS program, Synopsys will collaborate with other commercial and university experts, including Arm, Boeing, UltraSoC, University of Florida Institute for Cyber Security (FICS), Texas A&M University, and University of California San Diego.

The Fugaku supercomputer, which was jointly developed by RIKEN and Fujitsu Limited and based on Arm technology, was ranked number one on the TOP500 list of the world’s fastest supercomputers. In addition, it received top honors on the HPCG list, a ranking of benchmarks across real-world applications, the HPL-AI, which rates performance on tasks used in artificial intelligence applications, and Graph 500, which ranks systems based on data-intensive loads. It has also been named world’s most efficient supercomputer on the Green500 list in November 2019.

Synopsys achieved CarbonNeutral certification across its global operations for the second consecutive year, offsetting approximately 90,000 metric tons of carbon dioxide equivalent in 2020. The company also committed to reducing its greenhouse gas emissions by 25% by 2024, compared with its 2018 baseline.

Events
Many conferences have now been cancelled, postposed, or moved online. Find out what’s happening with each at our events page. How about checking out a webinar instead? Or check out our latest Chip Basics video, Different Levels Of Interconnects, which explains how different layers at the chip level can affect the performance across a system.

DAC will be a virtual event this year. It will still take place July 19 – 23, 2020. Watch what’s new in this year’s content and focus. Keynotes for the event will cover a system look at semiconductor technology, the RISC-V revolution, wafer-scale deep learning accelerators, and looking ahead to 6G.